
Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC® 970MP RISC Microprocessor
AppNote_970FX-MP_Differences_TOC.fm.1.0
November 15, 2006 
Page 3 of 25
1. Abstract  ....................................................................................................................... 9
2. Overview ......................................................................................................................  9
3. Processor Version Register (PVR) ............................................................................  9
4. General Parameters ..................................................................................................  10
5. Design Enhancements for PowerPC 970MP  .......................................................... 10
5.1 Dual Core Design ................................................................ ............................................................ 10
5.1.1 1MB L2 Cache per Core ...................................... ..................................................................  12
5.2 Processor Interconnect Bus ................... .........................................................................................  13
5.2.1 SCOM control and status registers ...................................................... .................................. 13
5.2.2 Test Modes ......................................... ...................................................................................  13
5.2.2.1 Transmitter Pseudo-Random Data Test (RDT) ............... ............................................... 13
5.2.2.2 Transmitter Electrical Shorts Test (EST) ......................... ............................................... 13
5.2.2.3 Receiver Electrical Shorts Test (REST)  .........................................................................  14
5.2.2.4 Receiver Random Data Self Test .......................... ......................................................... 15
5.2.3 Bus Configuration ......... .........................................................................................................  15
5.3 PowerTuning ............................. ......................................................................................................  17
5.3.1 Power Modes ....................................................................... .................................................. 17
5.3.2 Time Base and Decrementer ............................................ ..................................................... 1 8
5.4 I2C Bus Interface .............................................................. ...............................................................  18
5.4.1 Clock Dithering (New feature for 970FX DD3.0, enhanced in 970MP)  ..................... ............ 18
5.4.2 Programmable Delays for Power Saving Mode Transitions  ..................................................  19
5.5 Additional Dynamic Power Management  ........................................................................................ 19
5.6 More Precise Kelvin Circuitry ....... ...................................................................................................  19
7. Timings  ...................................................................................................................... 20
8. Package  ..................................................................................................................... 20
8.1 Design Considerations for a 970MP Thermal Solution  ...................................................................  20
8.1.1 Die Size  .................................................................................................................................  20
8.1.2 Capacitor Position  .................................................................................................. ............... 21
8.2 Description of Signal Changes ...................................... ..................................................................  21
8.3 PowerPC 970MP Microprocessor Package Dimensions  ................................................................  22
 Revision Log  ................................................................................................................ 25