Intel ATX Power Supply Design Guide

Version 0.9

3.4 Timing / Housekeeping / Control

PS_ON#Off

On

95%

+5VDC/+3.3VDC O/P 10%

T5

PWR_OK

T3

T2

PWR_OK Sense Level = 95% of nominal

~

~

~

T4

Figure 1: Power Supply Timing

Notes:

T2 is defined in Section 3.4.5.

T3, T4, and T5 are defined in Table 9.

3.4.1 PWR_OK

PWR_OK is a “power good” signal. It should be asserted high by the power supply to indicate that the +5VDC and +3.3VDC outputs are above the undervoltage thresholds listed in Section 3.2.1 and that sufficient mains energy is stored by the converter to guarantee continuous power operation within specification for at least the duration specified in Section 3.3.8. Conversely, PWR_OK should be deasserted to a low state when either the +5VDC or the +3.3VDC output voltages falls below the undervoltage threshold, or when mains power has been removed for a time sufficiently long such that power supply operation cannot be guaranteed beyond the hold-up time. The electrical and timing characteristics of the PWR_OK signal are given in Table 9 and in Figure 1.

Table 9: PWR_OK Signal Characteristics

Signal Type

Logic level low

Logic level high

High state output impedance

PWR_OK delay

PWR_OK rise time

Power down warning

+5 V TTL compatible

< 0.4 V while sinking 4 mA

Between 2.4 VDC and 5 VDC output while sourcing 200 µA

1KΩ from output to common

100 ms < T3 < 500 ms

T5 10 ms

T4 > 1 ms

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