Intel 2047285001R ESM-2850, 2.4.3.1.2 PCI Signals, 2.4.3.1.3 PCI Express Graphics Signals

ESM-2850

2.4.3.1.2 PCI Signals

Signal		Signal Description
PCI_AD[0:31]		PCI bus multiplexed address and data lines
PCI_PME#		PCI Power Management Event: PCI peripherals drive PME# to wake system from
		low-power states S1–S5.
PCI_GNT[0:3]#		PCI bus master grant output lines, active low.
PCI_REQ[0:3]#		PCI bus master request input lines, active low.
PCI_RESET#		PCI Reset output, active low.
PCI_CBE[0:3]		PCI bus byte enable lines, active low
PCI_PERR#		Parity Error: An external PCI device drives PERR# when it receives data that has a
		parity error.
PCI_LOCK#	PCI Lock control line, active low.
PCI_DEVSEL#		PCI bus Device Select, active low.
PCI_IRD Y#		PCI bus Initiator Ready control line, active low.
PCI_IRQ[A:D]		PCI interrupt request lines.
PCI_PAR	PCI bus parity
PCI_SERR#		System Error: SERR# can be pulsed active by any PCI device that detects a
		system error condition.
PCI_STOP#		PCI bus STOP control line, active low, driven by cycle initiator.
PCI_TRDY#		PCI bus Target Ready control line, active low.
PCI_FRAME#		PCI bus Frame control line, active low.
PCI_CLKRUN#		Bidirectional pin used to support PCI clock run protocol for mobile systems.
PCI_CLK	PCI 33MHz clock output.

2.4.3.1.3 PCI Express Graphics Signals

Signal	Signal Description
PEG_RX[0:15] +/-	PCI Express Graphics receive differential pairs. Some of these are multiplexed
	with SDVO lines (see SDVO section).
PEG_TX[0:15] +/-	PCI Express Graphics transmit differential pairs. Some of these are multiplexed
	with SDVO lines (see SDVO section).
TYPE[0:2]
PEG_LANE_RV#	PCI Express Graphics lane reversal input strap. Pull low to reverse lane order.
	Pulled high on module.
SDVO_DATA	SDVO I2C data line - to set up SDVO peripherals.
SDVO_CLK	SDVO I2C clock line - to set up SDVO peripherals.

38 ESM-2850 User’s Manual