82575 Ethernet Controller Design Guide

3.582575 Ethernet Controller Device Test Capability

The 82575 Ethernet Controller Gigabit Ethernet Controller contains a test access port (3.3 V only) conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment.

A BSDL (Boundary Scan Definition Language) file describing the 82575 Ethernet Controller device is available for use in your test environment.

The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR tree operation are available from your Intel representative.

Information about how to obtain test models is available from your Intel representative.

3.6PHY Functionality

This section describes various functions of the PHY.

3.6.1Auto Cross-over for MDI and MDI-X resolution

Twisted pair Ethernet PHY's must be correctly configured for MDI or MDI-X operation to interoperate. The PHY supports the automatic MDI/MDI-X configuration; manual (non- automatic) configuration is still possible by special cable, etc.

For 1000BASE-T links, pair identification is determined automatically in accordance with the standard.

For 10/100 links and during auto-negotiation, pair usage is determined by Bits 12 and 13 in the Port Control Register (PHYREG18).

In addition, the PHY has an Automatic Crossover Detection function. If Bit 18.12 = 1, the PHY automatically detects which application is being used and configures itself accordingly

 

 

 

Flat Cable

 

 

TX

A

TX

RX

A

TX

RX

B

RX

TX

B

RX

PHY

 

RJ45

 

RJ45

 

TX

C

TX

RX

C

RX

RX D

RX

TX

D

TX

MDI (DTE/NIC)

 

MDIX (switch)

Cross (1:0)=00

 

Cross (1:0)=01

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Intel 317698-001 manual Ethernet Controller Device Test Capability, PHY Functionality

317698-001 specifications

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