82575 Ethernet Controller Design Guide

The table below summarizes link speed as function of power management state, link speed control, and gigabit speed enabling:

 

 

Gigabit disable bits

 

Power

Low Power

Disable

 

Disable

 

 

 

Link Up

 

1000 in

PHY speed

Management

1000 (reg

 

(reg 25.1

 

non-D0a

negotiation

State

25.6)

 

& 2)

 

(reg 25.3)

 

 

 

 

 

 

 

 

 

 

PHY negotiates to

 

 

0

 

 

highest speed

 

 

 

 

advertised ("normal

 

 

 

 

 

 

 

 

 

 

operation")

 

0

 

 

X

PHY negotiates to

 

 

 

 

 

highest speed

 

 

1

 

 

advertised ("normal

 

 

 

 

 

operation"), excluding

 

 

 

 

 

1000

D0a

 

 

 

 

PHY goes through Low

 

 

0

 

 

Power Link Up (LPLU)

 

 

 

 

procedure, starting

 

 

 

 

 

 

 

 

 

 

with advertised values

 

1

 

 

X

PHY goes through

 

 

 

 

 

 

LPLU procedure,

 

 

 

 

 

 

 

1

 

 

starting with

 

 

 

 

advertised values.

 

 

 

 

 

 

 

 

 

 

Does not advertise

 

 

 

 

 

1000

 

 

 

 

 

PHY negotiates to

 

 

0

 

0

highest speed

 

 

 

 

 

advertised

 

0

0

 

1

PHY negotiates to

 

 

1

 

X

highest speed

 

 

 

advertised, excluding

Non-D0a

 

 

 

 

1000

 

 

 

 

PHY goes through

 

 

 

 

 

 

 

0

 

0

LPLU procedure,

 

 

 

 

 

starting at 10

 

1

 

 

 

PHY goes through

 

 

0

 

1

LPLU procedure,

 

 

 

starting at 10. Does

 

 

 

 

 

 

 

 

 

 

not advertise 1000

3.6.5Link Energy Detect

The PHY de-asserts the Link Energy Detect Bit (PHYREG 25.4) whenever energy is not detected on the link. This bit provides an indication of a cable becoming plugged or unplugged.

This bit is valid only if auto-negotiation is enabled.

In order to correctly deduce that there is no energy, this bit must read as zero for three consecutive reads each second.

3.6.6Polarity Correction

The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS_0/MDI_MINUS_0) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame markers, are received consecutively. If link pulses or data are not received for 96-130 ms, the polarity state is reset to a non-inverted state.

Automatic polarity correction may be disabled by setting Bit PHYREG.27.5

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Intel 317698-001 manual Link Energy Detect, Polarity Correction, 25.6 Reg

317698-001 specifications

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