Intel 317698-001 manual

Intel® 82575 Gigabit Ethernet Controller

Design Guide V1.00

June 2007

317698-001

Contents

Main ii Contents Page Revision History Page 1.0 Introduction 1.1 Scope 1.2 Reference Documents 2.0 PCI Express Port Connection to the Device 2.1 PCI Express Reference Clock 2.2 Other PCI Express Signals 2.3 Physical Layer Features 2.3.1 Link Width Configuration 2.3.2 Polarity Inversion 2.3.3 Lane Reversal 2.4 PCI Express Routing Page 3.0 Ethernet Component Design Guidelines 3.1 General Design Considerations for Ethernet Controllers 3.1.1 Clock Source 3.1.2 Magnetics for 1000 BASE-T 3.1.2.1 Magnetics Module Qualification Steps 3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet Controller 3.2.2 Serial EEPROM 3.2.2.1 General Regions 3.2.2.2 EEPROM-less Operation 3.2.2.3 SPI EEPROMs for 82575 Ethernet Controller Controller 3.2.3 EEPROM Map Information 3.2.3.1 EEUPDATE 3.2.4 FLASH 0 0xA 0X30 0x40 0x50 3.2.4.1 Flash Write Control 3.2.4.2 Flash Erase Control 3.3 SMBus and NC-SI 3.4 Power Supplies for the 82575 Ethernet Controller Controllers Figure 3. Example Switching Voltage Regulator for 1.0 V and 1.8 V rotalugeR gnihctiwS nwoD-petS v8.1 >- v3.3 )A5.2( v0.1=tuoV 2niVP 61 2DNGP 31 3.4.1 82575 Ethernet Controller Power Sequencing rotalugeR raeniL v0.1 >- v8.1 v8.1=tuoV Adj 1 Vout 2 W YY Y Y 3.4.1.1 Using Regulators With Enable Pins 3.4.2 82575 Ethernet Controller Device Power Supply Filtering 3.4.3 82575 Ethernet Controller Controller Power Management and Wake Up 3.4.4 Power Management 3.4.4.1 PCIe Power Management Dr D0u D0aD3 Page 3.5 82575 Ethernet Controller Device Test Capability 3.6 PHY Functionality 3.6.1 Auto Cross-over for MDI and MDI-X resolution 3.6.2 Smartspeed 3.6.2.1 Using SmartSpeed 3.6.3 Flow Control 3.6.4 Low-Power Link Up 3.6.5 Link Energy Detect 3.6.6 Polarity Correction 3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMII 3.6.8 Copper PHY Link Configuration 3.7 Copper/Fiber Switch 3.8 Device Disable 3.8.1 BIOS handling of Device Disable 3.9 Software-Definable Pins (SDPs) Page 4.0 Frequency Control Device Design Considerations 4.1 Frequency Control Component Types 4.1.1 Quartz Crystal 4.1.2 Fixed Crystal Oscillator 4.1.3 Programmable Crystal Oscillators 4.1.4 Ceramic Resonator 5.0 Crystal Selection Parameters 5.1 Vibrational Mode 5.2 Nominal Frequency 5.3 Frequency Tolerance 5.4 Temperature Stability and Environmental Requirements 5.5 Calibration Mode 5.6 Load Capacitance C C1 C2() C1 C2+() -------------------Cstray += 5.7 Shunt Capacitance 5.8 Equivalent Series Resistance 5.9 Drive Level 5.10 Aging 5.11 Reference Crystal 5.11.1 Reference Crystal Selection 5.11.2 Circuit Board 5.11.3 Temperature Changes Page 6.0 Oscillator Support 6.1 Oscillator Solution Page 7.0 Ethernet Component Layout Guidelines 7.1 Layout Considerations for 82575 Ethernet Controllers 7.1.1 Guidelines for Component Placement Page Page 7.1.2 Crystals and Oscillators 7.1.2.1 Crystal layout considerations 7.1.3 Board Stack Up Recommendations 7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs . 7.1.4.1 Signal Termination and Coupling 7.1.5 Signal Trace Geometry for 1000 BASE-T Designs 7.1.6 Trace Length and Symmetry for 1000 BASE-T Designs 7.1.6.1 Signal Detect 7.1.7 Routing 1.8 V to the Magnetics Center Tap 7.1.8 Impedance Discontinuities 7.1.9 Reducing Circuit Inductance 7.1.10 Signal Isolation 7.1.11 Power and Ground Planes 7.1.12 Traces for Decoupling Capacitors 7.1.13 Light Emitting Diodes for Designs Based on the 82575 Controller 7.1.14 Thermal Design Considerations 7.2 Physical Layer Conformance Testing 7.2.1 Conformance Tests for 10/100/1000 Mbps Designs 7.3 Troubleshooting Common Physical Layout Issues