Intel cPCI-7200 manual for Timer Pacer Generation, configuration

2.7 8254 for Timer Pacer Generation

8254 Timer/Counter

	CLK0	Timer 0
“H”	GATE0	OUT0
	CLK1	Timer 1
“H”
	GATE1	OUT1
4MHz Clock	CLK2	Timer 2
“H”		OUT2
	GATE2

Digital Input Timer Pacer

Digital Output Timer Pacer

Figure 2.4 8254 configuration

The internal timer/counter 8254 on the PCI-7200 is configured as above diagram (figure 2.4). User can use it to generate the timer pacer for both digital input and digital output trigger.

The digital input timer pacer is from OUT0 (Timer 0), and the digital output timer pacer is from OUT1 (Timer 1). Besides, Timer 0 and Timer 2 can be cascaded together to generate more timer pacer frequency for digital input. Also, the Timer 2 can be cascaded with Timer 1 for digital output.

pacer rate = 4 MHz / ( C0 * C2)

if Timer 0 & Timer 2 are cascaded

pacer rate = 4 MHz / C0

if timer 0 & Timer 2 are not cascaded

The maximum pacer signal rate of input and output are 4MHz/2=2Mhz. The minimum signal rate is 4MHz/65535/65535, which is a very slow frequency that user may never use it.

For example, if you wish to get a pacer rate 2.5 kHz, you can set C0 = 40 and C2 = 40. That is

2.5KHz = 4Mhz / (40 x 40)

Installation ∙ 15