Intel cPCI-7200, PCI-7200 t t, t

Operation Theorem • 27

4.5 Timing Characteristic

1. I_REQ as input data strobe (Rising Edge Active)

th ≥ 60ns tI ≥ 60ns tCYC ≥ 5 PCI CLK Cycle

ts ≥ 2ns tn ≥ 30ns

2. I_REQ as input data strobe (Falling Edge Active)

valid data

D10~DI31

valid data

IN_R I_REQ

tcyc

tlth

th ≥ 60ns tI ≥ 60ns tCYC ≥ 5 PCI CLK Cycle

ts ≥ 2ns tn ≥ 30ns

IN_ I_REQ

tcyc

valid data

D10~DI31

valid data

Contents

Main NuDAQ / NuIPC PCI-7200 / cPCI-7200 12MB/S High Speed Digital Input/ Output Card Users Guide Page Page Page Getting service from ADLINK Page Table of Contents Page Page How to Use This Guide Introduction 1.1 Applications 1.2 Features 1.3 Specifications Page 1.4 Software Supporting 1.4.1 Programming Library 1.4.2 PCIS-LVIEW: LabVIEW Driver 1.4.3 PCIS-VEE: HP-VEE Driver 1.4.4 DAQBenchTM: ActiveX Controls 1.4.5 DASYLabTM PRO 1.4.6 PCIS-DDE: DDE Server and InTouchTM Page Installation 2.1 What You Have 2.2 Unpacking 2.3 Device Installation for Windows Systems 2.4 cPCI/PCI-7200s Layout CN1 CN2 Page 2.5 Hardware Installation Outline 12 Installation 2.6 Connector Pin Assignments 2.6.1 PCI-7200 Pin Assignments Figure 2.2 CN1 Pin Assignments Page 14 Installation 2.6.2 cPCI-7200 Pin Assignments 2.7 8254 for Timer Pacer Generation Timer 1 Timer 0 Timer 2 4MHz Clock Registers Format 3.1 I/O Registers Format 3.2 Digital Input Register (BASE + 10) 3.3 Digital Output Register (BASE + 14) 3.4 DIO Status & Control Register (BASE + 18) Page 3.5 Interrupt Status & Control Register (BASE + 1C) Page Page 3.6 8254 Timer Registers (BASE + 0) Operation Theorem 4.1 Direct Program Control 4.2 Timer Pacer Mode Timer 0 Timer 1 Timer 2 8254 Timer/Counter 8254 Timer/Counter 4.3 External Clock Mode Digital Input FIFO 4.4 Handshaking O_REQ O_ACK 4.5 Timing Characteristic t t t t t t t t t 1 19ns t t t C/C++ Libraries 5.1 Libraries Installation 5.2 Programming Guide 5.2.1 Naming Convention 5.2.2 Data Types 5.3 _7200_Initial 5.4 _7200_Switch_Card_No 5.5 _7200_AUX_DI 5.6 _7200_AUX_DI_Channel 5.7 _7200_AUX_DO 5.8 _7200_AUX_DO_Channel 5.9 _7200_DI 5.10 _7200_DI_Channel 5.11 _7200_DO 5.12 _7200_DO_Channel 5.13 _7200_Alloc_DMA_Mem 5.14 _7200_Free_DMA_Mem 5.15 _7200_Alloc_DBDMA_Mem 5.16 _7200_Free_DBDMA_Mem 5.17 _7200_DI_DMA_Start Page Page 5.18 _7200_DI_DMA_Status 5.19 _7200_DI_DMA_Stop 5.20 _7200_DblBufferMode 5.21 _7200_CheckHalfReady 5.22 _7200_DblBufferTransfer 5.23 _7200_GetOverrunStatus 5.24 _7200_DO_DMA_Start 5.25 _7200_DO_DMA_Status 5.26 _7200_DO_DMA_Stop 5.27 _7200_DI_Timer 5.28 _7200_DO_Timer Page Double Buffer Mode Principle Page Limitation Product Warranty/Service