Intel cPCI-7200 manual ≥ 0ns ≥ 60ns ≥ 2 PCI CLK Cycle ≥ 1 PCI CLK Cycle

3.I_REQ & I_ACK Handshaking

						t5
IN I_REQ			t3		t4
IN I_ACK
D10~DI31		valid data					valid data
		t1		t2
t1 ≥ 0ns	t5	≥ 60ns				t3 ≥ 2 PCI CLK Cycle
t2 ≥ 0ns	t4	≥ 1 PCI CLK Cycle

Note: I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted until I_REQ de-asserts.

4.O_REQ as output data strobe

Out O_REQ

D00~D031

ts

th

tcyc

valid data valid data

ts ≥ 19ns th ≥ 2 PCI CLK Cycles Tcyc ≥ 500ns

28 ∙ Operation Theorem