Manuals / Intel / Computer Equipment / Computer Hardware

Intel IQ80332 manual External Interrupt Routing to Intel 80332 I/O Processor

Models: IQ80332

1 68

Download 68 pages 34.25 Kb

Page 30

Intel ® IQ80332 I/O Processor

Hardware Reference Section

3.5Interrupt Routing

The 80332 Interrupt routing.

Table 9. External Interrupt Routing to Intel® 80332 I/O Processor

Interrupt	System Resource

HPI#	Temperature Sensor, Header

S_INTA#	PCI-X Slot INTB#, Header

S_INTB#	PCI-X Slot INTC#, Header

S_INTC#	PCI-X Slot INTD#, Header

S_INTD#	PCI-X Slot INTA#, Header

P_INTA#	PCI-X Card Edge INTA#, Header

P_INTB#	PCI-X Card Edge INTB#, Header

P_INTC#	PCI-X Card Edge INTC#, Header

P_INTD#	PCI-X Card Edge INTD#, Header

30	Evaluation Platform Board Manual

Image 30

Intel IQ80332 manual External Interrupt Routing to Intel 80332 I/O Processor, Interrupt System Resource

Contents

Intel IQ80332 I/O Processor Evaluation Platform Board ManualIntel IQ80332 I/O Processor Evaluation Platform Board Manual Contents 6.3 2.2 Figures Examples Revision History Date Revision Description001 Initial Release Document Purpose and Scope Other Related DocumentsElectronic Information Electronic InformationComponent References Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80332 I/O Processor 231 Summary of Features Feature DefinitionKit Content Hardware InstallationFirst-Time Installation and Test Power Requirements Development Strategy Factory SettingsContents of the Flash Supported Tool BucketsRedHat RedBoot Target MonitorsHost Communications Examples Serial-UART CommunicationJtag Debug Communication Network Communication Network Communication ExampleCommunicating with RedBoot GNUPro GDB/InsightIntel IQ80332 I/O Processor Connecting with GDB GDB set remotebaudThis Page Left Intentionally Blank Functional Diagram Target MarketForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup Memory SubsystemFlash Memory Requirements Flash Memory RequirementsInterrupt Routing External Interrupt Routing to Intel 80332 I/O ProcessorInterrupt System Resource Peripheral Bus Features 80332 populates the peripheral bus as depicted by FigureFlash ROM Features Flash ROMNon-Volatile RAM Rotary SwitchUart Audio BuzzerBattery Status Battery Status Buffer RequirementsRead Name Description Write Debug Interface Console Serial PortJtag Debug Jtag PortJtag Port Pin-out Board Reset Scheme Reset Requirements/SchemesDefault Switch Settings of S7A1- Visual Switches and JumpersSwitch Summary Switch SummaryConnector Summary Jumper SummaryGeneral Purpose Input/Output Header Switch S6A1 BPCI-X Reset Detail Descriptions of Switches/JumpersSwitch S1C2 80332 Reset Switch S8A1 RotarySwitch S7A1-3 Retry Settings and Operation Mode S7A1-4 PCI-X Bus B Speed Enable Settings and Operation ModeS7A1-8 Operation Mode S7A1-9 Operation ModeS7A1-10 Operation Mode Jumper J7D1 Flash bit-width Jumper J1C1 Jtag ChainJumper J1D2 Uart Control Jumper J9D3 Buzzer Volume Control Jumper J7B4 SMBus HeaderDram Components on the Peripheral BusSoftware Reference Peripheral Bus Memory Map Address Range in Hex Size Data Bus Width DescriptionBoard Support Package BSP Examples Intel 80332 I/O Processor Memory MapRedBoot* Intel 80332 I/O Processor Memory Map RedBoot Intel 80332 I/O Processor FilesVirtual Address Physical Address Size Description RedBoot 80332 DDR Memory Initialization Sequence IQ80321 and IQ80332 Comparisons This Page Left Intentionally Blank Introduction PurposeRelated Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Using Breakpoints Displaying Source CodeSetting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware Breakpoints3 C.9.3 Exceptions/Trapping