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Intel IQ80332 manual Revision History, Date Revision Description, Initial Release

Models: IQ80332

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Intel ® IQ80332 I/O Processor Evaluation Platform Board Manual

Contents

Revision History

Date	Revision	Description

27 September 2004	001	Initial Release.

8

September, 2004

Document Number: 274069-001US

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Intel IQ80332 manual Revision History, Date Revision Description, Initial Release

Contents

Intel IQ80332 I/O Processor Evaluation Platform Board ManualIntel IQ80332 I/O Processor Evaluation Platform Board Manual Contents 6.3 2.2 Figures Examples 001 Initial Release Revision HistoryDate Revision Description Document Purpose and Scope Other Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80332 I/O Processor 231 Summary of Features Feature DefinitionFirst-Time Installation and Test Kit ContentHardware Installation Power Requirements Factory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedHat RedBoot Target MonitorsJtag Debug Communication Host Communications ExamplesSerial-UART Communication Network Communication Network Communication ExampleCommunicating with RedBoot GNUPro GDB/InsightIntel IQ80332 I/O Processor Connecting with GDB GDB set remotebaudThis Page Left Intentionally Blank Functional Diagram Target MarketForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup Memory SubsystemFlash Memory Requirements Flash Memory RequirementsInterrupt System Resource Interrupt RoutingExternal Interrupt Routing to Intel 80332 I/O Processor Peripheral Bus Features 80332 populates the peripheral bus as depicted by FigureFlash ROM Features Flash ROMRotary Switch UartNon-Volatile RAM Audio BuzzerRead Name Description Write Battery StatusBattery Status Buffer Requirements Debug Interface Console Serial PortJtag Port Pin-out Jtag DebugJtag Port Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryDefault Switch Settings of S7A1- Visual Switch SummaryGeneral Purpose Input/Output Header Connector SummaryJumper Summary Detail Descriptions of Switches/Jumpers Switch S1C2 80332 ResetSwitch S6A1 BPCI-X Reset Switch S8A1 RotarySwitch S7A1-3 Retry Settings and Operation Mode S7A1-4 PCI-X Bus B Speed Enable Settings and Operation ModeS7A1-10 Operation Mode S7A1-8 Operation ModeS7A1-9 Operation Mode Jumper J1D2 Uart Control Jumper J7D1 Flash bit-widthJumper J1C1 Jtag Chain Jumper J9D3 Buzzer Volume Control Jumper J7B4 SMBus HeaderDram Components on the Peripheral BusSoftware Reference Peripheral Bus Memory Map Address Range in Hex Size Data Bus Width DescriptionBoard Support Package BSP Examples Intel 80332 I/O Processor Memory MapVirtual Address Physical Address Size Description RedBoot* Intel 80332 I/O Processor Memory MapRedBoot Intel 80332 I/O Processor Files RedBoot 80332 DDR Memory Initialization Sequence IQ80321 and IQ80332 Comparisons This Page Left Intentionally Blank Introduction PurposeRelated Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeManually Loading and Executing an Application Program Launching and Configuring DebuggerRunning the CodeLab Debugger Using Breakpoints Displaying Source CodeSetting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware Breakpoints3 C.9.3 Exceptions/Trapping