Intel MIC-3358 user manual Delayed Transaction, 5 Integrated Peripherals setup screen

Models: MIC-3358

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Delayed Transaction

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI spec- ification version 2.1. The settings are: Enabled (Default) and Disabled.

4.1.5 Integrated Peripherals

Figure 4.5: Integrated Peripherals setup screen

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Intel MIC-3358 user manual Delayed Transaction, 5 Integrated Peripherals setup screen