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SB-6862
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SB-6862
The following table matches processor speed, processor clock
and the boardî‚’s processor bus speed:
Processor
Clock Ratio
Processor
Type/Speed
Bus Speed
180 MHz
3x
60 MHz
200 MHz
3x
66 MHz
Contents
Main
Page
Features
FCC Standards
Page
WARNING
NOTICE
1997 CSS Laboratories, Inc. All rights reserved.
Page
Table of Contents
Page
Overview
The Microprocessor
3SB-6862
The Board
Processor
DIMM
Figure 1: The Board
Dual Processor
Page
Board Connectors
Page
Page
Jumpers
Page
Page
System Memory
System Memory Configuration
Page
Page
System Memory Map
System Interrupts
The processor has two controllers, supplying 16 IRQs. Below are assignments in decreasing priority.
Direct Memory Access
The I/O Address Map
Configuration Utilities