Intel®
5.1.22.5” Pin Locations
Figure 7. Layout of Signal and Power Segment Pins
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Signal Segment S1 | Power Segment P1 | |||||||||||||||||||||||||||||||||||||||||||
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5.2Signal Description Table
Table 13. | Serial ATA Connector Pin Signal Definitions for 1.8” and 2.5” Form Factors | ||
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Pin |
| Function | Definition |
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S1 |
| Ground | 2nd mate |
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S2 |
| A+ | Differential signal pair A |
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S3 |
| A- | |
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S4 |
| Ground | 2nd mate |
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S5 |
| B- | Differential signal pair B |
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S6 |
| B+ | |
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S7 |
| Ground | 2nd mate |
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Note: Key and spacing separate signal and power segments. |
Table 14. | Serial ATA Power Pin Definitions for 1.8” Form Factor | ||||
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Pin |
| Function | Definition |
| Mating Order1 |
P1 |
| V | 3.3 V Power2 |
| 2nd Mate |
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| 33 |
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P2 |
| V | 3.3 V Power, |
| 1st Mate |
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| 33 |
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P3 |
| Ground3 |
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| 1st Mate |
P4 |
| Ground3 |
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| 1st Mate |
P5 |
| V | 5 V Power. Not connected4 |
| 1st Mate |
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| 5 |
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| Intel® | |
February 2009 |
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| Product Manual |
Order Number: |
| 17 |