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3. TECHNICAL BRIEF
3.2.2 Block Description
•Processing core
- TEAKLite DSP core
•
-32k Byte Boot ROM on the AHB
-96k Byte SRAM on the AHB, flexibly usable as program or data RAM
-16k Byte Cache for Program (internal)
-8k Byte tightly coupled memory for Program(internal)
-8k Byte Cache for Data(internal)
-8k Byte tightly coupled memory for Data(internal)
•
-104K x 16bit Program ROM
-8k x 16bit Program RAM
-60k x 16bit Data ROM
-37k x 16bit Data RAM
-Incremental Redundancy(IR) Memory of 35904 words of 16bit
•Shared Memory Block
1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.
•Controller Bus system
The processor cores and their peripherals are connected by powerful buses.
•Clock system
The clock system allows widely independent selection of frequencies for the essential parts of the
•Functional Hardware block
-CPU and DSP Timers
-MOVE coprocessor performing motion estimation for video encoding algorithms (H.263,
-Programmable PLL with additional phase shifters for system clock generation
-GSM Timer Module that
-GMSK /
-GMSK Modulator:
-EDGE Modulator:
-Hardware accelerators for equalizer and channel decoding.
-Incremental Redundancy memory for EDGE class 12 support
-A5/1, A5/2, A5/3 Cipher unit
-GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
-Advanced static and dynamic power management features including
-Pulse Number Modulation output for Automatic Frequency Correction(AFC)
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