Contents
Features
General Description
Applications
Ordering Information
Parameter Symbol Conditions MIN TYP MAX Units DC Accuracy
Dynamic Characteristics differential inputs
Analog Input INAP, INAN, INBP, Inbn
Conversion Rate
Parameter Symbol Conditions MIN TYP MAX Units
Internal Reference Refout
Interchannel Characteristics
Vcom
Clock Inputs CLKP, Clkn
DIFFCLK/ Seclk = GND, Clkn = GND
DIFFCLK/ Seclk = OV DD
Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4
Power Requirements
D0A-D13A, Dora
DIFFCLK/SECLK = GND
DIFFCLK/SECLK = Ovdd
Timing Characteristics Figure
Typical Operating Characteristics
FFT Plot 32,768-POINT Data Record
MAX12557
TWO-TONE IMD Plot 16,384-POINT Data Record
THD, Sfdr vs. Clock Speed
FIN = 70MHz, AIN = -0.5dBFS
FCLK = 65.00352MHz, fIN = 175MHz
PDISS, Iovdd Digital
Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz
SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS
Gain Error vs. Temperature
PIN Name Function
Pin Description
Same side of the PC board
D0B
D1B
D2B
D3B
Detailed Description
Shref
Refout
Refin
Functional Diagram
Reference Configurations
Reference Mode
Analog Inputs and Input Track-and-Hold T/H Amplifier
Reference Output
Clock Duty-Cycle Equalizer
Clock Input and Clock Control Lines
Data-Valid Output
System Timing Requirements
DIV4 DIV2 Function
Output Codes vs. Input Voltage
Power-Down Input
Vrefp Vrefn
Binary-to-Gray and Gray-to-Binary Code Conversion
Single-Ended AC-Coupled Input Signal
Using Transformer Coupling
Applications Information
Buffered External Reference Drives Multiple ADCs
Unbuffered External Reference Drives Multiple ADCs
Grounding, Bypassing, and Board Layout
MAX12557
Parameter Definitions
Aperture Delay
Full-Power Bandwidth
Overdrive Recovery Time
Total Harmonic Distortion THD
Gain Matching
Pin Configuration
Offset Matching
Package Information
68L QFN THIN.EPS