D0A-D13A, Dora, Power Requirements | Maxim MAX12557 instruction

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -0.5dBFS (differen- tial), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40°C to

+85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS

D0A–D13A, DORA,
D0B–D13B and DORB Tri-State	COUT			3		pF
Output Capacitance (Note 3)

DAV Tri-State Output	CDAV			6		pF
Capacitance (Note 3)	CDAV			6		pF
Capacitance (Note 3)

POWER REQUIREMENTS

Analog Supply Voltage	VDD		3.15	3.30	3.60	V
Digital Output Supply Voltage	OVDD		1.70	2.0	VDD	V
		Normal operating mode
		fIN = 175MHz at -0.5dBFS,		185
		single-ended clock		185
		single-ended clock
		(DIFFCLK/SECLK = GND)
Analog Supply Current	IVDD	Normal operating mode				mA
Analog Supply Current	IVDD	fIN = 175MHz at -0.5dBFS		193	210	mA
		fIN = 175MHz at -0.5dBFS
		differential clock
		differential clock
		(DIFFCLK/SECLK = OVDD)
		Power-down mode (PD = OVDD)		0.05
		clock idle		0.05
		clock idle

		Normal operating mode
		fIN = 175MHz at -0.5dBFS		610
		single-ended clock		610
		single-ended clock
		(DIFFCLK/SECLK = GND)
Analog Power Dissipation	PVDD	Normal operating mode				mW
Analog Power Dissipation	PVDD	fIN = 175MHz at -0.5dBFS		637	693	mW
		fIN = 175MHz at -0.5dBFS
		differential clock
		differential clock
		(DIFFCLK/SECLK = OVDD)
		Power-down mode (PD = OVDD)		0.165
		clock idle		0.165
		clock idle

		Normal operating mode		21.3
		fIN = 175MHz at -0.5dBFS		21.3
Digital Output Supply Current	IOVDD	fIN = 175MHz at -0.5dBFS				mA
Digital Output Supply Current	IOVDD	Power-down mode (PD = OVDD)		0.001		mA
		Power-down mode (PD = OVDD)
		clock idle
		clock idle

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Image 6

Maxim MAX12557 manual D0A-D13A, Dora, Power Requirements, Diffclk/Seclk = Gnd, DIFFCLK/SECLK = Ovdd

Contents

Applications FeaturesGeneral Description Ordering Information Analog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion Rate Parameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom DIFFCLK/ Seclk = OV DD Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 DIFFCLK/SECLK = GND Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = Ovdd Typical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record MAX12557 TWO-TONE IMD Plot 16,384-POINT Data Record THD, Sfdr vs. Clock Speed FIN = 70MHz, AIN = -0.5dBFS Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS Gain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D2B D0BD1B D3B Refout Detailed DescriptionShref Refin Functional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference Output Clock Duty-Cycle Equalizer Clock Input and Clock Control Lines System Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Power-Down Input Vrefp Vrefn Binary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCs Grounding, Bypassing, and Board Layout MAX12557 Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THD Pin Configuration Gain MatchingOffset Matching Package Information 68L QFN THIN.EPS