Power
Figure 13. Thread and Core C-State Entry and Exit
C0
MWAIT(C1), HLT |
| MWAIT(C7), |
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MWAIT(C1), HLT |
| P_LVL4 I/O Read |
| MWAIT(C6), | |
(C1E Enabled) | MWAIT(C3), | P_LVL3 I/O Read |
P_LVL2 I/O Read
C1 | C1E | C3 | C6 | C7 |
While individual threads can request
Table 18. | Coordination of Thread Power States at the Core Level |
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| Processor Core |
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| Thread 1 |
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| C0 | C1 | C3 | C6 |
| C7 |
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| C0 | C0 | C0 | C0 | C0 |
| C0 |
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| C1 | C0 | C11 | C11 | C11 |
| C11 |
| Thread 0 | C3 | C0 | C11 | C3 | C3 |
| C3 |
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| C6 | C0 | C11 | C3 | C6 |
| C6 |
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| C7 | C0 | C11 | C3 | C6 |
| C7 |
| Note: 1. If enabled, the core |
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4.2.3Requesting Low-Power Idle States
The primary software interfaces for requesting
For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT
The BIOS can write to the
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
December 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 53 |