|
| |
|
|
|
Signal Group | Type | Signals |
|
|
|
DDR3 / DDR3L Data Signals 2 |
| |
Single ended | DDR3/DDR3L Bi- | SA_DQ[63:0], SB_DQ[63:0] |
| directional |
|
|
|
|
Differential | DDR3/DDR3L Bi- | SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0] |
| directional |
|
|
|
|
DDR3 / DDR3L Compensation |
| |
|
|
|
| Analog Input | SM_RCOMP[2:0] |
|
|
|
DDR3 / DDR3L Reference Voltage Signals | ||
|
|
|
| DDR3/DDR3L | SM_VREF, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ |
| Output |
|
|
|
|
Testability (ITP/XDP) |
| |
|
|
|
Single ended | CMOS Input | TCK, TDI, TMS, TRST# |
|
|
|
Single ended | GTL | TDO |
|
|
|
Single ended | Output | DBR# |
|
|
|
Single ended | GTL | BPM#[7:0] |
|
|
|
Single ended | GTL | PREQ# |
|
|
|
Single ended | GTL | PRDY# |
|
|
|
Control Sideband |
|
|
|
|
|
Single ended | GTL Input/Open | PROCHOT# |
| Drain Output |
|
|
|
|
Single ended | Asynchronous | THERMTRIP#, IVR_ERROR |
| CMOS Output |
|
|
|
|
Single ended | GTL | CATERR# |
|
|
|
Single ended | Asynchronous | PM_SYNC,RESET#, PWRGOOD, PWR_DEBUG# |
| CMOS Input |
|
|
|
|
Single ended | Asynchronous Bi- | PECI |
| directional |
|
|
|
|
Single ended | GTL | CFG[19:0] |
|
|
|
Single ended | Analog Input | SM_RCOMP[2:0] |
|
|
|
Voltage Regulator |
|
|
|
|
|
Single ended | CMOS Input | VR_READY |
|
|
|
Single ended | CMOS Input | VIDALERT# |
|
|
|
Single ended | Open Drain Output | VIDSCLK |
|
|
|
Single ended | GTL Input/Open | VIDSOUT |
| Drain Output |
|
|
|
|
Differential | Analog Output | VCC_SENSE, VSS_SENSE |
|
|
|
Power / Ground / Other |
| |
|
|
|
Single ended | Power | VCC, VDDQ |
|
|
|
| Ground | VSS, VSS_NCTF 3 |
| No Connect | RSVD, RSVD_NCTF |
|
|
|
|
| continued... |
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
Datasheet – Volume 1 of 2 96