Table 49. | VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM |
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| Symbol | Parameter | Typ |
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| VCCIO_OUT | Termination | 1.0 |
| — | V |
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| ICCIO_OUT | Maximum | — |
| 300 | mA |
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| External Load |
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| VCOMP_OUT | Termination | 1.0 |
| — | V | 1 |
| Voltage |
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| VCCIO_TERM | Termination | 1.0 |
| — | V | 2 |
| Voltage |
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| Notes: 1. VCOMP_OUT may only be used to connect to PEG_RCOMP and DP_RCOMP. |
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| 2. Internal processor power for signal termination. |
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Table 50. | DDR3 / DDR3L Signal Group DC Specifications |
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| Symbol | Parameter | Min | Typ | Max | Units | Notes1 |
| VIL | Input Low Voltage | — | VDDQ/2 | 0.43*VDDQ | V | 2, 4, 11 |
| VIH | Input High Voltage | 0.57*VDDQ | VDDQ/2 | — | V | 3, 11 |
| VIL | Input Low Voltage | — | — | 0.15*VDDQ | V | — |
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| VIH | Input High Voltage | 0.45*VDDQ | — | 1.0 | V | 10, 12 |
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| DDR3/DDR3L Data |
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| RON_UP(DQ) | Buffer | 20 | 26 | 32 | Ω | 5, 11 |
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| DDR3/DDR3L Data |
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| RON_DN(DQ) | Buffer | 20 | 26 | 32 | Ω | 5, 11 |
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| DDR3/DDR3L |
| 50 | 62 | Ω | 11 |
| RODT(DQ) | termination equivalent | 38 |
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| resistance for data |
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| DDR3/DDR3L |
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| VODT(DC) | termination DC working | 0.45*VDDQ | 0.5*VDDQ | 0.55*VDDQ | V | 11 |
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| receive mode) |
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| DDR3/DDR3L Clock |
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| 5, 11, |
| RON_UP(CK) | Buffer | 20 | 26 | 32 | Ω | |
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| DDR3/DDR3L Clock |
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| 5, 11, |
| RON_DN(CK) | Buffer | 20 | 26 | 32 | Ω | |
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| DDR3/DDR3L Command |
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| 5, 11, |
| RON_UP(CMD) | Buffer | 15 | 20 | 25 | Ω | |
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| DDR3/DDR3L Command |
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| 5, 11, |
| RON_DN(CMD) | Buffer | 15 | 20 | 25 | Ω | |
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| DDR3/DDR3L Control |
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| 5, 11, |
| RON_UP(CTL) | Buffer | 19 | 25 | 31 | Ω | |
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| Resistance |
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| continued... | |
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
Datasheet – Volume 1 of 2 100
