Intel BX80646I54570S, CM8064601466200, BX80646I74770 DDR3 / DDR3L System Memory Timing Support

December 2013 Order No.: 328897-004

Processor—Interfaces

Raw	DIMM	DRAM	DRAM	# of	# of	# of	# of	Page Size
Card	Capacity	Device	Organization	DRAM	Physical	Row / Col	Banks
Version		Technology		Devices	Devices	Address	Inside
					Ranks	Bits	DRAM
	2 GB	1 Gb	128 M X 8	16	2	14/10	8	8K
B	4 GB	2 Gb	256 M X 8	16	2	15/10	8	8K
	4 GB	4 Gb	512 M X 8	8	1	15/10	8	8K
	8 GB	4 Gb	512 M X 8	16	2	16/10	8	8K

Note: DIMM module support is based on availability and is subject to change.

Table 5.	Supported SO-DIMM Module Configurations (AIO Only)
Raw Card	DIMM	DRAM	# of DRAM	# of Row/Col	# of Banks	Page Size
Version	Capacity	Organization	Devices	Address Bits	Inside DRAM
	1 GB	128 M x 8	8	14/10	8	8K
B	2 GB	256 M x 8	8	15/10	8	8K
	4 GB	512 M x 8	8	16/10	8	8K
	2 GB	128 M x 8	16	14/10	8	8K
F
	4 GB	256 M x 8	16	15/10	8	8K
	8 GB	512 M x 8	16	16/10	8	8K

Note: System memory configurations are based on availability and are subject to change.

2.1.2System Memory Timing Support

The IMC supports the following DDR3/DDR3L Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

•tCL = CAS Latency

•tRCD = Activate Command to READ or WRITE Command delay

•tRP = PRECHARGE Command Period

•CWL = CAS Write Latency

•Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

Table 6.	DDR3 / DDR3L System Memory Timing Support
	Segment	Transfer Rate	tCL (tCK)	tRCD	tRP	CWL	DPC	CMD
		(MT/s)		(tCK)	(tCK)	(tCK)		Mode
		1333	8/9	8/9	8/9	7	1	1N/2N
	All segments						2	2N
		1600	10/11	10/11	10/11	8	1	1N/2N
							2	2N

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

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