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Intel BX80646I54570S, CM8064601466200 continued, Processor Ball and Signal Information-Processor

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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Processor Ball and Signal Information—Processor

	Signal Name	Ball #		Signal Name	Ball #		Signal Name	Ball #

	DPLL_REF_CLKN	W6		PEG_RXP14	K5		PEG_TXP4	C8

	DPLL_REF_CLKP	W5		PEG_RXP15	L4		PEG_TXP5	B7

	EDP_DISP_UTIL	E16		PEG_RXP2	E13		PEG_TXP6	A6

	FC_K9	K9		PEG_RXP3	D12		PEG_TXP7	B5

	FC_Y7	Y7		PEG_RXP4	E11		PEG_TXP8	E1

	FDI_CSYNC	D16		PEG_RXP5	F10		PEG_TXP9	F2

	FDI0_TX0N0	B14		PEG_RXP6	E9		PM_SYNC	P36

	FDI0_TX0N1	C13		PEG_RXP7	F8		PRDY#	L39

	FDI0_TX0P0	A14		PEG_RXP8	D3		PREQ#	L37

	FDI0_TX0P1	B13		PEG_RXP9	E4		PROCHOT#	K38

	IST_TRIGGER	C39		PEG_TXN0	B12		PWR_DEBUG	N40

	IVR_ERROR	R36		PEG_TXN1	C11		PWRGOOD	AB35

	PECI	N37		PEG_TXN10	G2		RESET#	M39

	PEG_RCOMP	P3		PEG_TXN11	H3		RSVD	AB33

	PEG_RXN0	F15		PEG_TXN12	J2		RSVD	AB36

	PEG_RXN1	E14		PEG_TXN13	K3		RSVD	AB8

	PEG_RXN10	F6		PEG_TXN14	M3		RSVD	AC8

	PEG_RXN11	G5		PEG_TXN15	L2		RSVD	AK20

	PEG_RXN12	H6		PEG_TXN2	D10		RSVD	AL20

	PEG_RXN13	J5		PEG_TXN3	C9		RSVD	AT40

	PEG_RXN14	K6		PEG_TXN4	D8		RSVD	AU1

	PEG_RXN15	L5		PEG_TXN5	C7		RSVD	AU27

	PEG_RXN2	F13		PEG_TXN6	B6		RSVD	AU39

	PEG_RXN3	E12		PEG_TXN7	C5		RSVD	AV2

	PEG_RXN4	F11		PEG_TXN8	E2		RSVD	AV20

	PEG_RXN5	G10		PEG_TXN9	F3		RSVD	AV24

	PEG_RXN6	F9		PEG_TXP0	A12		RSVD	AV29

	PEG_RXN7	G8		PEG_TXP1	B11		RSVD	AW12

	PEG_RXN8	D4		PEG_TXP10	G1		RSVD	AW23

	PEG_RXN9	E5		PEG_TXP11	H2		RSVD	AW24

	PEG_RXP0	E15		PEG_TXP12	J1		RSVD	AW27

	PEG_RXP1	D14		PEG_TXP13	K2		RSVD	AY18

	PEG_RXP10	F5		PEG_TXP14	M2		RSVD	H12

	PEG_RXP11	G4		PEG_TXP15	L1		RSVD	H14

	PEG_RXP12	H5		PEG_TXP2	C10		RSVD	H15

	PEG_RXP13	J4		PEG_TXP3	B9		RSVD	J15

		continued...			continued...			continued...

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	111

Image 111

Intel BX80646I54570S, CM8064601466200, CM8064601466003 manual continued, Processor Ball and Signal Information-Processor

Contents

December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 1.0 Introduction Contents4.0 Power Management Revision History6.0 Signal Description Processor-Contents5.0 Thermal Management 7.8.1 Platform Environment Control Interface PECI DC Characteristics 7.0 Electrical Specifications8.0 Package Mechanical Specifications 9.0 Processor Ball and Signal InformationFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 IntroductionPlatform Controller Hub PCH Figure 1. Platform Block Diagram1.1 Supported Technologies ProcessorSystem 1.3 Power Management Support1.2 Interfaces Processor CoreTerminology 1.4 Thermal Management Support1.5 Package Support 1.6 Terminologywith Virtual Machine Monitor software, enables multiple, robust independent software Processor-Introductioncontinued continued Introduction-ProcessorTerm DescriptionDocument 1.7 Related DocumentsRelated Documents Processor-IntroductionDocument specificationsIntroduction-Processor Document2.1 System Memory Interface 2.0 InterfacesSupported UDIMM Module Configurations 2.1.1 System Memory Technology SupportedProcessor DIMM Support by Product Supported SO-DIMM Module Configurations AIO Only 2.1.2 System Memory Timing SupportDDR3 / DDR3L System Memory Timing Support 2.1.3 System Memory Organization Modes Single-Channel ModeDual-Channel Mode - Intel Flex Memory Technology Mode Dual-Channel Symmetric Mode2.1.3.1 System Memory Frequency 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsJust-in-Time Command Scheduling Command Overlap2.1.3.3 Data Scrambling Table 7. PCI Express* Supported Configurations in Desktop Products2.2 PCI Express* Interface 2.2.1 PCI Express* Support2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Related Register Structures in the Processor PCI Express* PortPCI Express* Lanes Connection 1 X 8 Controller 2.3 Direct Media Interface DMIFigure 4. PCI Express* Typical Operation 16 Lanes Mapping 1 X 4 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics3D Engine Execution Units Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics Processing 3D PipelineStrips and Fans SF Stage Vertex Shader VS StageGeometry Shader GS Stage Clip Stage2.6 Digital Display Interface DDI 2.5.2 Multi Graphics Controllers Multi-Monitor SupportLogical 128-Bit Fixed BLT and 256 Fill Engine Figure 6. Processor Display Architecture Figure 7. DisplayPort* Overview Source DeviceSink Device DisplayPortHDMI Tx HDMI SourceHDMI Sink Figure 8. HDMI* OverviewTable 8. Processor Supported Audio Formats over HDMI*and DisplayPort Multiple Display Configurationsembedded DisplayPort Integrated AudioHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.7 Intel Flexible Display Interface Intel FDI 2.8 Platform Environmental Control Interface PECI2.8.1 PECI Bus Architecture PECI Client Figure 9. PECI Host-Clients Connection ExamplePECI Host / Originatoring=VT 3.0 Technologies3.1 Intel Virtualization Technology Intel VT Intel VT-x ObjectivesIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology 3.4 Intel Turbo Boost Technology 3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2Intel Turbo Boost Technology 2.0 Frequency 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NI PCLMULQDQ InstructionIntel Secure Key 3.8 Intel 64 Architecture x2APIC 3.9 Power Aware Interrupt Routing PAIR 3.10 Execute Disable Bit3.11 Supervisor Mode Execution Protection SMEP S0 - Processor Fully powered on full on mode / connected standby mode 4.0 Power ManagementFigure 11. Processor Power States Note Power states availability may vary between the different SKUsIntegrated Memory Controller States 4.1 Advanced Configuration and Power Interface ACPI States SupportedSystem States Processor Core / Package State SupportG, S, and C Interface State Combinations 4.2 Processor Core Power Management4.2.1 Enhanced Intel SpeedStep Technology Key Features Direct Media Interface DMI StatesThread 4.2.2 Low-Power Idle StatesFigure 12. Idle Power Management Breakdown of the Processor Cores Thread4.2.3 Requesting Low-Power Idle States Coordination of Thread Power States at the Core LevelFigure 13. Thread and Core C-State Entry and Exit Core C3 State 4.2.4 Core C-State RulesCore C0 State Core C1/C1E StateC-State Auto-Demotion 4.2.5 Package C-StatesCore C6 State Core C7 StateCoordination of Core Power States at the Package Level Figure 14. Package C-State Entry and Exit Package C0 StatePackage C1/C1E State Package C7 State Package C2 StatePackage C3 State Package C6 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.3 Dynamic Power-Down 4.3.2.1 Initialization Role of CKE4.3.2.2 Conditional Self-Refresh 4.3.4 DDR Electrical Power Gating EPG 4.4 PCI Express* Power Management4.5 Direct Media Interface DMI Power Management 4.3.3 DRAM Running Average Power Limitation RAPL4.6.3 Intel Graphics Dynamic Frequency 4.6 Graphics Power Management4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6.2 Graphics Render C-StateThermal Management-Processor 5.0 Thermal ManagementProcessor-Thermal Management Desktop Processor Thermal Specifications5.1 Desktop Processor Thermal Profiles Temperature on pageCase 5.1.1 Processor PCG 2013D Thermal ProfileTCASE = 0.33 * Power + TTV Power Wcontinued 5.1.2 Processor PCG 2013C Thermal ProfileProcessor-Thermal Management continued5.1.3 Processor PCG 2013B Thermal Profile Thermal Management-Processorcontinued Processor-Thermal Management 5.1.4 Processor PCG 2013A Thermal Profile37.5 37.5 5.2 Thermal Metrology5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS Measure TCASE at the geometric center of the packageΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS 5.5 Processor Temperature Figure 21. Digital Thermal Sensor DTS Thermal Profile DefinitionThermal Margin Slope Frequency Control 5.6 Adaptive Thermal MonitorCritical Temperature Flag Clock ModulationImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.9.1 Intel Turbo Boost Technology Power Control and Reporting 5.9 Intel Turbo Boost Technology Thermal Considerations5.8.1 Digital Thermal Sensor Accuracy Taccuracy Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power ControlMemory Channel A Signals 6.0 Signal Description6.1 System Memory Interface Signals Signal Description Buffer Typescontinued Memory Channel B SignalsSignal Description-Processor Write Enable Control Signal This signal is used withDDR3/DDR3L Reference Voltage This signal is used as 6.2 Memory Reference and Compensation SignalsMemory Reference and Compensation Signals Processor-Signal DescriptionCFG3 MSR Privacy Bit Feature 6.3 Reset and Miscellaneous SignalsReset and Miscellaneous Signals Signal Description-ProcessorDisplay Interface Signals 6.4 PCI Express*-Based Interface Signals6.5 Display Interface Signals PCI Express* Graphics Interface SignalsTestability Signals 6.7 Phase Locked Loop PLL Signals6.8 Testability Signals Phase Locked Loop PLL SignalsPower Sequencing Signals 6.9 Error and Thermal Protection Signals6.10 Power Sequencing Signals Error and Thermal Protection SignalsProcessor Power Signals 6.11 Processor Power Signals6.12 Sense Signals 6.13 Ground and Non-Critical to Function NCTF Signals7.3 VCC Voltage Identification VID 7.0 Electrical Specifications7.2 Power and Ground Lands 7.1 Integrated Voltage Regulatorcontinued Table 45. Voltage Regulator VR 12.5 Voltage IdentificationElectrical Specifications-Processor continuedProcessor-Electrical Specifications continuedcontinued Electrical Specifications-Processor continuedcontinued continued Processor-Electrical Specifications7.4 Reserved or Unused Signals 7.5 Signal GroupsSignal Groups DDR3 / DDR3L Compensation DDR3 / DDR3L Data SignalsDDR3 / DDR3L Reference Voltage Signals Power / Ground / OtherDigital Media Interface DMI 7.6 Test Access Port TAP Connection7.7 DC Specifications PCI Express* Graphics7.8 Voltage and Current Specifications Processor-Electrical Specificationscontinued Electrical Specifications-Processor continued DDR3 / DDR3L Signal Group DC SpecificationsVCCIOOUT, VCOMPOUT, and VCCIOTERM Processor-Electrical SpecificationsElectrical Specifications-Processor Digital Display Interface Group DC SpecificationsProcessor-Electrical Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications GTL Signal Group and Open Drain Signal Group DC Specificationscontinued 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsPCI Express* DC Specifications Electrical Specifications-Processor7.8.2 Input Device Hysteresis Figure 23. Input Device HysteresisProcessor-Electrical Specifications 8.1 Processor Component Keep-Out Zone 8.0 Package Mechanical Specifications8.2 Package Loading Specifications Figure 24. Processor Package Assembly Sketch8.3 Package Handling Guidelines 8.4 Package Insertion Specifications8.5 Processor Mass Specification Processor Loading SpecificationsFigure 25. Processor Top-Side Markings 8.7 Processor Markings8.8 Processor Land Coordinates Processor MaterialsProcessor-Package Mechanical Specifications 8.9 Processor Storage SpecificationsProcessor Storage Specifications Figure 26. Processor Package Land CoordinatesPackage Mechanical Specifications-Processor RHsustained storageTIMEsustained storage Processor Ball List by Signal Name 9.0 Processor Ball and Signal Informationcontinued Processor Ball and Signal Information-Processorcontinued continuedcontinued Processor-Processor Ball and Signal Informationcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameAU20 continuedcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal Name