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Intel BX80646I74770, CM8064601466200 continued, Processor-Processor Ball and Signal Information

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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December 2013 Order No.: 328897-004

				Processor—Processor Ball and Signal Information

Signal Name	Ball #		Signal Name		Ball #		Signal Name	Ball #

RSVD	J17		RSVD_TP		P37		SA_DQ20	AM37

RSVD	J40		SA_BS0		AV12		SA_DQ21	AM38

RSVD	J9		SA_BS1		AY11		SA_DQ22	AP37

RSVD	L10		SA_BS2		AT21		SA_DQ23	AP40

RSVD	L12		SA_CAS#		AU9		SA_DQ24	AV37

RSVD	M10		SA_CK0		AY15		SA_DQ25	AW37

RSVD	M11		SA_CK1		AW15		SA_DQ26	AU35

RSVD	M38		SA_CK2		AV14		SA_DQ27	AV35

RSVD	N35		SA_CK3		AW13		SA_DQ28	AT37

RSVD	P33		SA_CKE0		AV22		SA_DQ29	AU37

RSVD	R33		SA_CKE1		AT23		SA_DQ3	AF39

RSVD	R34		SA_CKE2		AU22		SA_DQ30	AT35

RSVD	T34		SA_CKE3		AU23		SA_DQ31	AW35

RSVD	T35		SA_CKN0		AY16		SA_DQ32	AY6

RSVD	T8		SA_CKN1		AV15		SA_DQ33	AU6

RSVD	U8		SA_CKN2		AW14		SA_DQ34	AV4

RSVD	W8		SA_CKN3		AY13		SA_DQ35	AU4

RSVD	Y8		SA_CS#0		AU14		SA_DQ36	AW6

RSVD_TP	A4		SA_CS#1		AV9		SA_DQ37	AV6

RSVD_TP	AV1		SA_CS#2		AU10		SA_DQ38	AW4

RSVD_TP	AW2		SA_CS#3		AW8		SA_DQ39	AY4

RSVD_TP	B3		SA_DIMM_VREF		AB39		SA_DQ4	AD37
			DQ
RSVD_TP	C2		DQ				SA_DQ40	AR1

			SA_DQ0		AD38

RSVD_TP	D1						SA_DQ41	AR4

			SA_DQ1		AD39

RSVD_TP	H16						SA_DQ42	AN3

			SA_DQ10		AK38

RSVD_TP	J10						SA_DQ43	AN4

			SA_DQ11		AK39

RSVD_TP	J12						SA_DQ44	AR2

			SA_DQ12		AH37

RSVD_TP	J13						SA_DQ45	AR3

			SA_DQ13		AH38

RSVD_TP	J16						SA_DQ46	AN2

			SA_DQ14		AK37

RSVD_TP	J8						SA_DQ47	AN1

			SA_DQ15		AK40

RSVD_TP	K11						SA_DQ48	AL1

			SA_DQ16		AM40

RSVD_TP	K12						SA_DQ49	AL4

			SA_DQ17		AM39

RSVD_TP	K13						SA_DQ5	AD40

			SA_DQ18		AP38

RSVD_TP	K8						SA_DQ50	AJ3

			SA_DQ19		AP39

RSVD_TP	N36						SA_DQ51	AJ4

			SA_DQ2		AF38

RSVD_TP	N38						SA_DQ52	AL2

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Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 112

Image 112

Intel BX80646I74770, CM8064601466200, CM8064601466003 manual continued, Processor-Processor Ball and Signal Information

Contents

Datasheet - Volume 1 of DecemberDatasheet - Volume 1 of 2 Contents 4.0 Power ManagementRevision History 1.0 IntroductionProcessor-Contents 6.0 Signal Description5.0 Thermal Management 7.0 Electrical Specifications 8.0 Package Mechanical Specifications9.0 Processor Ball and Signal Information 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables Tables-ProcessorProcessor-Tables Revision History Revision History-Processor1.0 Introduction Processor-IntroductionFigure 1. Platform Block Diagram 1.1 Supported TechnologiesProcessor Platform Controller Hub PCH1.3 Power Management Support 1.2 InterfacesProcessor Core System1.4 Thermal Management Support 1.5 Package Support1.6 Terminology TerminologyProcessor-Introduction with Virtual Machine Monitor software, enables multiple, robust independent softwarecontinued Introduction-Processor TermDescription continued1.7 Related Documents Related DocumentsProcessor-Introduction Documentspecifications Introduction-ProcessorDocument Document2.0 Interfaces 2.1 System Memory Interface2.1.1 System Memory Technology Supported Supported UDIMM Module ConfigurationsProcessor DIMM Support by Product 2.1.2 System Memory Timing Support Supported SO-DIMM Module Configurations AIO OnlyDDR3 / DDR3L System Memory Timing Support Single-Channel Mode Dual-Channel Mode - Intel Flex Memory Technology ModeDual-Channel Symmetric Mode 2.1.3 System Memory Organization Modes2.1.3.2 Intel Fast Memory Access Intel FMA Technology Enhancements Just-in-Time Command SchedulingCommand Overlap 2.1.3.1 System Memory FrequencyTable 7. PCI Express* Supported Configurations in Desktop Products 2.2 PCI Express* Interface2.2.1 PCI Express* Support 2.1.3.3 Data Scrambling2.2.3 PCI Express* Configuration Mechanism 2.2.2 PCI Express* ArchitecturePCI Express* Port PCI Express* Related Register Structures in the ProcessorPCI Express* Lanes Connection 2.3 Direct Media Interface DMI Figure 4. PCI Express* Typical Operation 16 Lanes Mapping1 X 4 Controller 1 X 8 ControllerDMI Error Flow DMI Link Down2.4 Processor Graphics 2.5 Processor Graphics Controller GTFigure 5. Processor Graphics Controller Unit Block Diagram 2.5.1 3D and Video Engines for Graphics Processing3D Pipeline 3D Engine Execution UnitsVertex Shader VS Stage Geometry Shader GS StageClip Stage Strips and Fans SF Stage2.5.2 Multi Graphics Controllers Multi-Monitor Support 2.6 Digital Display Interface DDILogical 128-Bit Fixed BLT and 256 Fill Engine Figure 6. Processor Display Architecture Source Device Sink DeviceDisplayPort Figure 7. DisplayPort* OverviewHDMI Source HDMI SinkFigure 8. HDMI* Overview HDMI TxMultiple Display Configurations embedded DisplayPortIntegrated Audio Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortValid Three Display Configurations through the Processor High-bandwidth Digital Content Protection HDCP2.8 Platform Environmental Control Interface PECI 2.7 Intel Flexible Display Interface Intel FDI2.8.1 PECI Bus Architecture Figure 9. PECI Host-Clients Connection Example PECIHost / Originator PECI Client3.0 Technologies 3.1 Intel Virtualization Technology Intel VTIntel VT-x Objectives ing=VTIntel VT-x Features Intel VT-d Objectives Intel VT-d Features Figure 10. Device to Domain Mapping Structures3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology 3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 3.4 Intel Turbo Boost TechnologyIntel Turbo Boost Technology 2.0 Frequency PCLMULQDQ Instruction 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIIntel Secure Key 3.8 Intel 64 Architecture x2APIC 3.10 Execute Disable Bit 3.9 Power Aware Interrupt Routing PAIR3.11 Supervisor Mode Execution Protection SMEP 4.0 Power Management Figure 11. Processor Power StatesNote Power states availability may vary between the different SKUs S0 - Processor Fully powered on full on mode / connected standby mode4.1 Advanced Configuration and Power Interface ACPI States Supported System StatesProcessor Core / Package State Support Integrated Memory Controller States4.2 Processor Core Power Management 4.2.1 Enhanced Intel SpeedStep Technology Key FeaturesDirect Media Interface DMI States G, S, and C Interface State Combinations4.2.2 Low-Power Idle States Figure 12. Idle Power Management Breakdown of the Processor CoresThread ThreadCoordination of Thread Power States at the Core Level 4.2.3 Requesting Low-Power Idle StatesFigure 13. Thread and Core C-State Entry and Exit 4.2.4 Core C-State Rules Core C0 StateCore C1/C1E State Core C3 State4.2.5 Package C-States Core C6 StateCore C7 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Package C0 State Figure 14. Package C-State Entry and ExitPackage C1/C1E State Package C2 State Package C3 StatePackage C6 State Package C7 State4.2.6 Package C-States and Display Resolutions Deepest Package C-State Available4.3 Integrated Memory Controller IMC Power Management 4.3.1 Disabling Unused System Memory Outputs4.3.2 DRAM Power Management and Initialization No power-down CKE disable4.3.2.1 Initialization Role of CKE 4.3.2.3 Dynamic Power-Down4.3.2.2 Conditional Self-Refresh 4.4 PCI Express* Power Management 4.5 Direct Media Interface DMI Power Management4.3.3 DRAM Running Average Power Limitation RAPL 4.3.4 DDR Electrical Power Gating EPG4.6 Graphics Power Management 4.6.1 Intel Rapid Memory Power Management Intel RMPM4.6.2 Graphics Render C-State 4.6.3 Intel Graphics Dynamic Frequency5.0 Thermal Management Thermal Management-ProcessorDesktop Processor Thermal Specifications 5.1 Desktop Processor Thermal ProfilesTemperature on page Processor-Thermal Management5.1.1 Processor PCG 2013D Thermal Profile TCASE = 0.33 * Power +TTV Power W Case5.1.2 Processor PCG 2013C Thermal Profile Processor-Thermal Managementcontinued continuedThermal Management-Processor 5.1.3 Processor PCG 2013B Thermal Profilecontinued 5.1.4 Processor PCG 2013A Thermal Profile Processor-Thermal Management5.2 Thermal Metrology 5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTSMeasure TCASE at the geometric center of the package 37.5 37.5Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Figure 21. Digital Thermal Sensor DTS Thermal Profile Definition 5.5 Processor TemperatureThermal Margin Slope 5.6 Adaptive Thermal Monitor Frequency ControlClock Modulation Critical Temperature FlagImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.7 THERMTRIP# Signal 5.8 Digital Thermal Sensor5.9 Intel Turbo Boost Technology Thermal Considerations 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.2 Package Power Control Intel Turbo Boost Technology 2.0 Package Power Control SettingsFigure 22. Package Power Control 5.9.3 Turbo Time Parameter6.0 Signal Description 6.1 System Memory Interface SignalsSignal Description Buffer Types Memory Channel A SignalsMemory Channel B Signals Signal Description-ProcessorWrite Enable Control Signal This signal is used with continued6.2 Memory Reference and Compensation Signals Memory Reference and Compensation SignalsProcessor-Signal Description DDR3/DDR3L Reference Voltage This signal is used as6.3 Reset and Miscellaneous Signals Reset and Miscellaneous SignalsSignal Description-Processor CFG3 MSR Privacy Bit Feature6.4 PCI Express*-Based Interface Signals 6.5 Display Interface SignalsPCI Express* Graphics Interface Signals Display Interface Signals6.7 Phase Locked Loop PLL Signals 6.8 Testability SignalsPhase Locked Loop PLL Signals Testability Signals6.9 Error and Thermal Protection Signals 6.10 Power Sequencing SignalsError and Thermal Protection Signals Power Sequencing Signals6.11 Processor Power Signals 6.12 Sense Signals6.13 Ground and Non-Critical to Function NCTF Signals Processor Power Signals7.0 Electrical Specifications 7.2 Power and Ground Lands7.1 Integrated Voltage Regulator 7.3 VCC Voltage Identification VIDTable 45. Voltage Regulator VR 12.5 Voltage Identification Electrical Specifications-Processorcontinued continuedcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued Processor-Electrical Specifications continued7.5 Signal Groups 7.4 Reserved or Unused SignalsSignal Groups DDR3 / DDR3L Data Signals DDR3 / DDR3L Reference Voltage SignalsPower / Ground / Other DDR3 / DDR3L Compensation7.6 Test Access Port TAP Connection 7.7 DC SpecificationsPCI Express* Graphics Digital Media Interface DMIProcessor-Electrical Specifications 7.8 Voltage and Current Specificationscontinued Electrical Specifications-Processor DDR3 / DDR3L Signal Group DC Specifications VCCIOOUT, VCOMPOUT, and VCCIOTERMProcessor-Electrical Specifications continuedDigital Display Interface Group DC Specifications Electrical Specifications-Processorembedded DisplayPort* eDP* Group DC Specifications CMOS Signal Group DC SpecificationsGTL Signal Group and Open Drain Signal Group DC Specifications Processor-Electrical Specifications7.8.1 Platform Environment Control Interface PECI DC Characteristics PCI Express* DC SpecificationsElectrical Specifications-Processor continuedFigure 23. Input Device Hysteresis 7.8.2 Input Device HysteresisProcessor-Electrical Specifications 8.0 Package Mechanical Specifications 8.2 Package Loading SpecificationsFigure 24. Processor Package Assembly Sketch 8.1 Processor Component Keep-Out Zone8.4 Package Insertion Specifications 8.5 Processor Mass SpecificationProcessor Loading Specifications 8.3 Package Handling Guidelines8.7 Processor Markings 8.8 Processor Land CoordinatesProcessor Materials Figure 25. Processor Top-Side Markings8.9 Processor Storage Specifications Processor Storage SpecificationsFigure 26. Processor Package Land Coordinates Processor-Package Mechanical SpecificationsRHsustained storage Package Mechanical Specifications-ProcessorTIMEsustained storage 9.0 Processor Ball and Signal Information Processor Ball List by Signal NameProcessor Ball and Signal Information-Processor continuedcontinued continuedProcessor-Processor Ball and Signal Information continuedcontinued continuedSignal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #continued continuedcontinued AU20Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #