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Intel CM8064601466200, BX80646I74770 Input Device Hysteresis, Processor-Electrical Specifications

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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7.8.2Input Device Hysteresis

December 2013 Order No.: 328897-004

Processor—Electrical Specifications

	Symbol	Definition and Conditions	Min	Max	Units	Notes1
	Vn	Negative-Edge Threshold	0.275 *	0.500	V	—
	Vn	Voltage	VCCIO_TERM	* VCCIO_TERM	V	—
		Voltage	VCCIO_TERM	* VCCIO_TERM

	Vp	Positive-Edge Threshold	0.550 *	0.725 *	V	—
	Vp	Voltage	VCCIO_TERM	VCCIO_TERM	V	—
		Voltage	VCCIO_TERM	VCCIO_TERM

	Cbus	Bus Capacitance per Node	N/A	10	pF	—

	Cpad	Pad Capacitance	0.7	1.8	pF	—

	Ileak000	leakage current at 0 V	—	0.6	mA	—

	Ileak025	leakage current at 0.25*	—	0.4	mA	—
	Ileak025	VCCIO_TERM	—	0.4	mA	—
		VCCIO_TERM

	Ileak050	leakage current at 0.50*	—	0.2	mA	—
	Ileak050	VCCIO_TERM	—	0.2	mA	—
		VCCIO_TERM

	Ileak075	leakage current at 0.75*	—	0.13	mA	—
	Ileak075	VCCIO_TERM	—	0.13	mA	—
		VCCIO_TERM

	Ileak100	leakage current at	—	0.10	mA	—
	Ileak100	VCCIO_TERM	—	0.10	mA	—
		VCCIO_TERM

	Notes: 1. VCCIO_TERM supplies the PECI interface. PECI behavior does not affect VCCIO_TERM minimum /
	maximum specifications.
	2. The leakage specification applies to powered devices on the PECI bus.
	3. The PECI buffer internal pull-up resistance measured at 0.75* VCCIO_TERM .

7.8.2Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.

Figure 23. Input Device Hysteresis

VTTD

Maximum VP

PECI High Range

Minimum VP

Minimum

Valid Input

Hysteresis

Signal Range

Maximum VN

Minimum VN

PECI Low Range

PECI Ground

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 104

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Intel CM8064601466200, CM8064601466003, BX80637I73770K manual Input Device Hysteresis, Processor-Electrical Specifications

Contents

Datasheet - Volume 1 of DecemberDatasheet - Volume 1 of 2 Contents 4.0 Power ManagementRevision History 1.0 Introduction5.0 Thermal Management 6.0 Signal DescriptionProcessor-Contents 7.0 Electrical Specifications 8.0 Package Mechanical Specifications9.0 Processor Ball and Signal Information 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables Tables-ProcessorProcessor-Tables Revision History Revision History-Processor1.0 Introduction Processor-IntroductionFigure 1. Platform Block Diagram 1.1 Supported TechnologiesProcessor Platform Controller Hub PCH1.3 Power Management Support 1.2 InterfacesProcessor Core System1.4 Thermal Management Support 1.5 Package Support1.6 Terminology Terminologycontinued with Virtual Machine Monitor software, enables multiple, robust independent softwareProcessor-Introduction Introduction-Processor TermDescription continued1.7 Related Documents Related DocumentsProcessor-Introduction Documentspecifications Introduction-ProcessorDocument Document2.0 Interfaces 2.1 System Memory InterfaceProcessor DIMM Support by Product Supported UDIMM Module Configurations2.1.1 System Memory Technology Supported DDR3 / DDR3L System Memory Timing Support Supported SO-DIMM Module Configurations AIO Only2.1.2 System Memory Timing Support Single-Channel Mode Dual-Channel Mode - Intel Flex Memory Technology ModeDual-Channel Symmetric Mode 2.1.3 System Memory Organization Modes2.1.3.2 Intel Fast Memory Access Intel FMA Technology Enhancements Just-in-Time Command SchedulingCommand Overlap 2.1.3.1 System Memory FrequencyTable 7. PCI Express* Supported Configurations in Desktop Products 2.2 PCI Express* Interface2.2.1 PCI Express* Support 2.1.3.3 Data Scrambling2.2.3 PCI Express* Configuration Mechanism 2.2.2 PCI Express* ArchitecturePCI Express* Lanes Connection PCI Express* Related Register Structures in the ProcessorPCI Express* Port 2.3 Direct Media Interface DMI Figure 4. PCI Express* Typical Operation 16 Lanes Mapping1 X 4 Controller 1 X 8 ControllerDMI Error Flow DMI Link Down2.4 Processor Graphics 2.5 Processor Graphics Controller GTFigure 5. Processor Graphics Controller Unit Block Diagram 2.5.1 3D and Video Engines for Graphics Processing3D Pipeline 3D Engine Execution UnitsVertex Shader VS Stage Geometry Shader GS StageClip Stage Strips and Fans SF StageLogical 128-Bit Fixed BLT and 256 Fill Engine 2.6 Digital Display Interface DDI2.5.2 Multi Graphics Controllers Multi-Monitor Support Figure 6. Processor Display Architecture Source Device Sink DeviceDisplayPort Figure 7. DisplayPort* OverviewHDMI Source HDMI SinkFigure 8. HDMI* Overview HDMI TxMultiple Display Configurations embedded DisplayPortIntegrated Audio Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortValid Three Display Configurations through the Processor High-bandwidth Digital Content Protection HDCP2.8.1 PECI Bus Architecture 2.7 Intel Flexible Display Interface Intel FDI2.8 Platform Environmental Control Interface PECI Figure 9. PECI Host-Clients Connection Example PECIHost / Originator PECI Client3.0 Technologies 3.1 Intel Virtualization Technology Intel VTIntel VT-x Objectives ing=VTIntel VT-x Features Intel VT-d Objectives Intel VT-d Features Figure 10. Device to Domain Mapping Structures3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology Intel Turbo Boost Technology 2.0 Frequency 3.4 Intel Turbo Boost Technology3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 Intel Secure Key 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIPCLMULQDQ Instruction 3.8 Intel 64 Architecture x2APIC 3.11 Supervisor Mode Execution Protection SMEP 3.9 Power Aware Interrupt Routing PAIR3.10 Execute Disable Bit 4.0 Power Management Figure 11. Processor Power StatesNote Power states availability may vary between the different SKUs S0 - Processor Fully powered on full on mode / connected standby mode4.1 Advanced Configuration and Power Interface ACPI States Supported System StatesProcessor Core / Package State Support Integrated Memory Controller States4.2 Processor Core Power Management 4.2.1 Enhanced Intel SpeedStep Technology Key FeaturesDirect Media Interface DMI States G, S, and C Interface State Combinations4.2.2 Low-Power Idle States Figure 12. Idle Power Management Breakdown of the Processor CoresThread ThreadFigure 13. Thread and Core C-State Entry and Exit 4.2.3 Requesting Low-Power Idle StatesCoordination of Thread Power States at the Core Level 4.2.4 Core C-State Rules Core C0 StateCore C1/C1E State Core C3 State4.2.5 Package C-States Core C6 StateCore C7 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Package C1/C1E State Figure 14. Package C-State Entry and ExitPackage C0 State Package C2 State Package C3 StatePackage C6 State Package C7 State4.2.6 Package C-States and Display Resolutions Deepest Package C-State Available4.3 Integrated Memory Controller IMC Power Management 4.3.1 Disabling Unused System Memory Outputs4.3.2 DRAM Power Management and Initialization No power-down CKE disable4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power-Down4.3.2.1 Initialization Role of CKE 4.4 PCI Express* Power Management 4.5 Direct Media Interface DMI Power Management4.3.3 DRAM Running Average Power Limitation RAPL 4.3.4 DDR Electrical Power Gating EPG4.6 Graphics Power Management 4.6.1 Intel Rapid Memory Power Management Intel RMPM4.6.2 Graphics Render C-State 4.6.3 Intel Graphics Dynamic Frequency5.0 Thermal Management Thermal Management-ProcessorDesktop Processor Thermal Specifications 5.1 Desktop Processor Thermal ProfilesTemperature on page Processor-Thermal Management5.1.1 Processor PCG 2013D Thermal Profile TCASE = 0.33 * Power +TTV Power W Case5.1.2 Processor PCG 2013C Thermal Profile Processor-Thermal Managementcontinued continuedcontinued 5.1.3 Processor PCG 2013B Thermal ProfileThermal Management-Processor 5.1.4 Processor PCG 2013A Thermal Profile Processor-Thermal Management5.2 Thermal Metrology 5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTSMeasure TCASE at the geometric center of the package 37.5 37.5Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Thermal Margin Slope 5.5 Processor TemperatureFigure 21. Digital Thermal Sensor DTS Thermal Profile Definition 5.6 Adaptive Thermal Monitor Frequency ControlImmediate Transition to Combined TM1 and TM2 Critical Temperature FlagClock Modulation PROCHOT# Signal 5.7 THERMTRIP# Signal 5.8 Digital Thermal Sensor5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.9 Intel Turbo Boost Technology Thermal Considerations 5.9.2 Package Power Control Intel Turbo Boost Technology 2.0 Package Power Control SettingsFigure 22. Package Power Control 5.9.3 Turbo Time Parameter6.0 Signal Description 6.1 System Memory Interface SignalsSignal Description Buffer Types Memory Channel A SignalsMemory Channel B Signals Signal Description-ProcessorWrite Enable Control Signal This signal is used with continued6.2 Memory Reference and Compensation Signals Memory Reference and Compensation SignalsProcessor-Signal Description DDR3/DDR3L Reference Voltage This signal is used as6.3 Reset and Miscellaneous Signals Reset and Miscellaneous SignalsSignal Description-Processor CFG3 MSR Privacy Bit Feature6.4 PCI Express*-Based Interface Signals 6.5 Display Interface SignalsPCI Express* Graphics Interface Signals Display Interface Signals6.7 Phase Locked Loop PLL Signals 6.8 Testability SignalsPhase Locked Loop PLL Signals Testability Signals6.9 Error and Thermal Protection Signals 6.10 Power Sequencing SignalsError and Thermal Protection Signals Power Sequencing Signals6.11 Processor Power Signals 6.12 Sense Signals6.13 Ground and Non-Critical to Function NCTF Signals Processor Power Signals7.0 Electrical Specifications 7.2 Power and Ground Lands7.1 Integrated Voltage Regulator 7.3 VCC Voltage Identification VIDTable 45. Voltage Regulator VR 12.5 Voltage Identification Electrical Specifications-Processorcontinued continuedcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued Processor-Electrical Specifications continuedSignal Groups 7.4 Reserved or Unused Signals7.5 Signal Groups DDR3 / DDR3L Data Signals DDR3 / DDR3L Reference Voltage SignalsPower / Ground / Other DDR3 / DDR3L Compensation7.6 Test Access Port TAP Connection 7.7 DC SpecificationsPCI Express* Graphics Digital Media Interface DMIcontinued 7.8 Voltage and Current SpecificationsProcessor-Electrical Specifications Electrical Specifications-Processor DDR3 / DDR3L Signal Group DC Specifications VCCIOOUT, VCOMPOUT, and VCCIOTERMProcessor-Electrical Specifications continuedDigital Display Interface Group DC Specifications Electrical Specifications-Processorembedded DisplayPort* eDP* Group DC Specifications CMOS Signal Group DC SpecificationsGTL Signal Group and Open Drain Signal Group DC Specifications Processor-Electrical Specifications7.8.1 Platform Environment Control Interface PECI DC Characteristics PCI Express* DC SpecificationsElectrical Specifications-Processor continuedProcessor-Electrical Specifications 7.8.2 Input Device HysteresisFigure 23. Input Device Hysteresis 8.0 Package Mechanical Specifications 8.2 Package Loading SpecificationsFigure 24. Processor Package Assembly Sketch 8.1 Processor Component Keep-Out Zone8.4 Package Insertion Specifications 8.5 Processor Mass SpecificationProcessor Loading Specifications 8.3 Package Handling Guidelines8.7 Processor Markings 8.8 Processor Land CoordinatesProcessor Materials Figure 25. Processor Top-Side Markings8.9 Processor Storage Specifications Processor Storage SpecificationsFigure 26. Processor Package Land Coordinates Processor-Package Mechanical SpecificationsTIMEsustained storage Package Mechanical Specifications-ProcessorRHsustained storage 9.0 Processor Ball and Signal Information Processor Ball List by Signal NameProcessor Ball and Signal Information-Processor continuedcontinued continuedProcessor-Processor Ball and Signal Information continuedcontinued continuedSignal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #continued continuedcontinued AU20Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #