Intel BX80646I54570S, BX80646I74770 Reset and Miscellaneous Signals, Signal Description-Processor

Signal Description—Processor

6.3Reset and Miscellaneous Signals

Table 33.	Reset and Miscellaneous Signals
	Signal Name		Description	Direction /
				Buffer Type
		Configuration Signals: The CFG signals have a default value of
		'1' if not terminated on the board.
		• CFG[1:0]: Reserved configuration lane. A test point may be
		placed on the board for these lanes.
		• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
		—	1 = Normal operation
		— 0 = Lane numbers reversed.
		• CFG[3]: MSR Privacy Bit Feature
		— 1 = Debug capability is determined by
			IA32_Debug_Interface_MSR (C80h) bit[0] setting	I/O
	CFG[19:0]	—	0 = IA32_Debug_Interface_MSR (C80h) bit[0] default
				GTL
			setting overridden
		• CFG[4]: Reserved configuration lane. A test point may be
		placed on the board for this lane.
		• CFG[6:5]: PCI Express* Bifurcation: 1
		—	00 = 1 x8, 2 x4 PCI Express*
		—	01 = reserved
		—	10 = 2 x8 PCI Express*
		—	11 = 1 x16 PCI Express*
		• CFG[19:7]: Reserved configuration lanes. A test point may
		be placed on the board for these lands.
	CFG_RCOMP	Configuration resistance compensation. Use a 49.9 Ω ±1%		—
		resistor to ground.
		FC (Future Compatibility) signals are signals that are available for
	FC_x	compatibility with other processors. A test point may be placed
		on the board for these lands.
	PM_SYNC	Power Management Sync: A sideband signal to communicate		I
		power management status from the platform to the processor.		CMOS
	PWR_DEBUG#	Signal is for debug.		I
				Asynchronous
				CMOS
	IST_TRIGGER	Signal is for IFDIM testing only.		I
				CMOS
		Signal is for debug. If both THERMTRIP# and this signal are		O
	IVR_ERROR	simultaneously asserted, the processor has encountered an
		unrecoverable power delivery fault and has engaged automatic		CMOS
		shutdown as a result.
	RESET#	Platform Reset pin driven by the PCH.		I
				CMOS
	RSVD	RESERVED: All signals that are RSVD and RSVD_NCTF must be		No Connect
		left unconnected on the board. Intel recommends that all		Test Point
	RSVD_TP
		RSVD_TP signals have via test points.		Non-Critical to
	RSVD_NCTF
				Function
	SM_DRAMRST#	DRAM Reset: Reset signal from processor to DRAM devices. One		O
		signal common to all channels.		CMOS
	TESTLO_x	TESTLO should be individually connected to VSS through a
		resistor.
	Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	85