Manuals / Intel / Computer Equipment / Computer Hardware

Intel BX80646I74770S, CM8064601466200, CM8064601466003, BX80637I73770K, CM8063701212200 manual Figures

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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December 2013 Order No.: 328897-004

	Processor—Figures
Figures
1	Platform Block Diagram	11
2	Intel® Flex Memory Technology Operations	21
3	PCI Express* Related Register Structures in the Processor	25
4	PCI Express* Typical Operation 16 Lanes Mapping	26
5	Processor Graphics Controller Unit Block Diagram	29
6	Processor Display Architecture	32
7	DisplayPort* Overview	33
8	HDMI* Overview	34
9	PECI Host-Clients Connection Example	38
10	Device to Domain Mapping Structures	42
11	Processor Power States	49
12	Idle Power Management Breakdown of the Processor Cores	52
13	Thread and Core C-State Entry and Exit	53
14	Package C-State Entry and Exit	57
15	Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D)	67
16	Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C)	68
17	Thermal Test Vehicle Thermal Profile for Processor (PCG 2013B)	69
18	Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A)	70
19	Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location	71
20	Digital Thermal Sensor (DTS) 1.1 Definition Points	72
21	Digital Thermal Sensor (DTS) Thermal Profile Definition	74
22	Package Power Control	81
23	Input Device Hysteresis	104
24	Processor Package Assembly Sketch	105
25	Processor Top-Side Markings	107
26	Processor Package Land Coordinates	108

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 6

Image 6

Intel BX80646I74770S, CM8064601466200, CM8064601466003, BX80637I73770K, CM8063701212200, CM8063701159502, BX80646I54430 Figures

Contents

Datasheet - Volume 1 of DecemberDatasheet - Volume 1 of 2 Revision History Contents4.0 Power Management 1.0 Introduction6.0 Signal Description Processor-Contents5.0 Thermal Management 9.0 Processor Ball and Signal Information 7.0 Electrical Specifications8.0 Package Mechanical Specifications 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables Tables-ProcessorProcessor-Tables Revision History Revision History-Processor1.0 Introduction Processor-IntroductionProcessor Figure 1. Platform Block Diagram1.1 Supported Technologies Platform Controller Hub PCHProcessor Core 1.3 Power Management Support1.2 Interfaces System1.6 Terminology 1.4 Thermal Management Support1.5 Package Support Terminologywith Virtual Machine Monitor software, enables multiple, robust independent software Processor-Introductioncontinued Description Introduction-ProcessorTerm continuedProcessor-Introduction 1.7 Related DocumentsRelated Documents DocumentDocument specificationsIntroduction-Processor Document2.0 Interfaces 2.1 System Memory InterfaceSupported UDIMM Module Configurations 2.1.1 System Memory Technology SupportedProcessor DIMM Support by Product Supported SO-DIMM Module Configurations AIO Only 2.1.2 System Memory Timing SupportDDR3 / DDR3L System Memory Timing Support Dual-Channel Symmetric Mode Single-Channel ModeDual-Channel Mode - Intel Flex Memory Technology Mode 2.1.3 System Memory Organization ModesCommand Overlap 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsJust-in-Time Command Scheduling 2.1.3.1 System Memory Frequency2.2.1 PCI Express* Support Table 7. PCI Express* Supported Configurations in Desktop Products2.2 PCI Express* Interface 2.1.3.3 Data Scrambling2.2.3 PCI Express* Configuration Mechanism 2.2.2 PCI Express* ArchitecturePCI Express* Related Register Structures in the Processor PCI Express* PortPCI Express* Lanes Connection 1 X 4 Controller 2.3 Direct Media Interface DMIFigure 4. PCI Express* Typical Operation 16 Lanes Mapping 1 X 8 ControllerDMI Error Flow DMI Link Down2.4 Processor Graphics 2.5 Processor Graphics Controller GT3D Pipeline Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics Processing 3D Engine Execution UnitsClip Stage Vertex Shader VS StageGeometry Shader GS Stage Strips and Fans SF Stage2.6 Digital Display Interface DDI 2.5.2 Multi Graphics Controllers Multi-Monitor SupportLogical 128-Bit Fixed BLT and 256 Fill Engine Figure 6. Processor Display Architecture DisplayPort Source DeviceSink Device Figure 7. DisplayPort* OverviewFigure 8. HDMI* Overview HDMI SourceHDMI Sink HDMI TxIntegrated Audio Multiple Display Configurationsembedded DisplayPort Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortValid Three Display Configurations through the Processor High-bandwidth Digital Content Protection HDCP2.7 Intel Flexible Display Interface Intel FDI 2.8 Platform Environmental Control Interface PECI2.8.1 PECI Bus Architecture Host / Originator Figure 9. PECI Host-Clients Connection ExamplePECI PECI ClientIntel VT-x Objectives 3.0 Technologies3.1 Intel Virtualization Technology Intel VT ing=VTIntel VT-x Features Intel VT-d Objectives Intel VT-d Features Figure 10. Device to Domain Mapping Structures3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology 3.4 Intel Turbo Boost Technology 3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2Intel Turbo Boost Technology 2.0 Frequency 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NI PCLMULQDQ InstructionIntel Secure Key 3.8 Intel 64 Architecture x2APIC 3.9 Power Aware Interrupt Routing PAIR 3.10 Execute Disable Bit3.11 Supervisor Mode Execution Protection SMEP Note Power states availability may vary between the different SKUs 4.0 Power ManagementFigure 11. Processor Power States S0 - Processor Fully powered on full on mode / connected standby modeProcessor Core / Package State Support 4.1 Advanced Configuration and Power Interface ACPI States SupportedSystem States Integrated Memory Controller StatesDirect Media Interface DMI States 4.2 Processor Core Power Management4.2.1 Enhanced Intel SpeedStep Technology Key Features G, S, and C Interface State CombinationsThread 4.2.2 Low-Power Idle StatesFigure 12. Idle Power Management Breakdown of the Processor Cores Thread4.2.3 Requesting Low-Power Idle States Coordination of Thread Power States at the Core LevelFigure 13. Thread and Core C-State Entry and Exit Core C1/C1E State 4.2.4 Core C-State RulesCore C0 State Core C3 StateCore C7 State 4.2.5 Package C-StatesCore C6 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Figure 14. Package C-State Entry and Exit Package C0 StatePackage C1/C1E State Package C6 State Package C2 StatePackage C3 State Package C7 State4.2.6 Package C-States and Display Resolutions Deepest Package C-State Available4.3 Integrated Memory Controller IMC Power Management 4.3.1 Disabling Unused System Memory Outputs4.3.2 DRAM Power Management and Initialization No power-down CKE disable4.3.2.3 Dynamic Power-Down 4.3.2.1 Initialization Role of CKE4.3.2.2 Conditional Self-Refresh 4.3.3 DRAM Running Average Power Limitation RAPL 4.4 PCI Express* Power Management4.5 Direct Media Interface DMI Power Management 4.3.4 DDR Electrical Power Gating EPG4.6.2 Graphics Render C-State 4.6 Graphics Power Management4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6.3 Intel Graphics Dynamic Frequency5.0 Thermal Management Thermal Management-ProcessorTemperature on page Desktop Processor Thermal Specifications5.1 Desktop Processor Thermal Profiles Processor-Thermal ManagementTTV Power W 5.1.1 Processor PCG 2013D Thermal ProfileTCASE = 0.33 * Power + Casecontinued 5.1.2 Processor PCG 2013C Thermal ProfileProcessor-Thermal Management continued5.1.3 Processor PCG 2013B Thermal Profile Thermal Management-Processorcontinued 5.1.4 Processor PCG 2013A Thermal Profile Processor-Thermal ManagementMeasure TCASE at the geometric center of the package 5.2 Thermal Metrology5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS 37.5 37.5Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS 5.5 Processor Temperature Figure 21. Digital Thermal Sensor DTS Thermal Profile DefinitionThermal Margin Slope 5.6 Adaptive Thermal Monitor Frequency ControlCritical Temperature Flag Clock ModulationImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.7 THERMTRIP# Signal 5.8 Digital Thermal Sensor5.9.1 Intel Turbo Boost Technology Power Control and Reporting 5.9 Intel Turbo Boost Technology Thermal Considerations5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.2 Package Power Control Intel Turbo Boost Technology 2.0 Package Power Control SettingsFigure 22. Package Power Control 5.9.3 Turbo Time ParameterSignal Description Buffer Types 6.0 Signal Description6.1 System Memory Interface Signals Memory Channel A SignalsWrite Enable Control Signal This signal is used with Memory Channel B SignalsSignal Description-Processor continuedProcessor-Signal Description 6.2 Memory Reference and Compensation SignalsMemory Reference and Compensation Signals DDR3/DDR3L Reference Voltage This signal is used asSignal Description-Processor 6.3 Reset and Miscellaneous SignalsReset and Miscellaneous Signals CFG3 MSR Privacy Bit FeaturePCI Express* Graphics Interface Signals 6.4 PCI Express*-Based Interface Signals6.5 Display Interface Signals Display Interface SignalsPhase Locked Loop PLL Signals 6.7 Phase Locked Loop PLL Signals6.8 Testability Signals Testability SignalsError and Thermal Protection Signals 6.9 Error and Thermal Protection Signals6.10 Power Sequencing Signals Power Sequencing Signals6.13 Ground and Non-Critical to Function NCTF Signals 6.11 Processor Power Signals6.12 Sense Signals Processor Power Signals7.1 Integrated Voltage Regulator 7.0 Electrical Specifications7.2 Power and Ground Lands 7.3 VCC Voltage Identification VIDcontinued Table 45. Voltage Regulator VR 12.5 Voltage IdentificationElectrical Specifications-Processor continuedProcessor-Electrical Specifications continuedcontinued Electrical Specifications-Processor continuedcontinued Processor-Electrical Specifications continued7.4 Reserved or Unused Signals 7.5 Signal GroupsSignal Groups Power / Ground / Other DDR3 / DDR3L Data SignalsDDR3 / DDR3L Reference Voltage Signals DDR3 / DDR3L CompensationPCI Express* Graphics 7.6 Test Access Port TAP Connection7.7 DC Specifications Digital Media Interface DMI7.8 Voltage and Current Specifications Processor-Electrical Specificationscontinued Electrical Specifications-Processor Processor-Electrical Specifications DDR3 / DDR3L Signal Group DC SpecificationsVCCIOOUT, VCOMPOUT, and VCCIOTERM continuedDigital Display Interface Group DC Specifications Electrical Specifications-ProcessorGTL Signal Group and Open Drain Signal Group DC Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications Processor-Electrical SpecificationsElectrical Specifications-Processor 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsPCI Express* DC Specifications continued7.8.2 Input Device Hysteresis Figure 23. Input Device HysteresisProcessor-Electrical Specifications Figure 24. Processor Package Assembly Sketch 8.0 Package Mechanical Specifications8.2 Package Loading Specifications 8.1 Processor Component Keep-Out ZoneProcessor Loading Specifications 8.4 Package Insertion Specifications8.5 Processor Mass Specification 8.3 Package Handling GuidelinesProcessor Materials 8.7 Processor Markings8.8 Processor Land Coordinates Figure 25. Processor Top-Side MarkingsFigure 26. Processor Package Land Coordinates 8.9 Processor Storage SpecificationsProcessor Storage Specifications Processor-Package Mechanical SpecificationsPackage Mechanical Specifications-Processor RHsustained storageTIMEsustained storage 9.0 Processor Ball and Signal Information Processor Ball List by Signal Namecontinued Processor Ball and Signal Information-Processorcontinued continuedcontinued Processor-Processor Ball and Signal Informationcontinued continuedSignal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #continued continuedcontinued AU20Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #