|
|
|
|
|
|
|
|
| |||
Figure 3. | PCI Express* Related Register Structures in the Processor |
| |||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
| Bridge |
|
|
| PCI |
|
|
|
|
|
|
|
|
|
|
|
| ||
|
| PCI | PEG0 |
| representing |
|
|
| Compatible |
|
|
|
| Express* |
| root PCI |
|
|
| Host Bridge |
|
| |
|
|
|
|
|
|
|
|
| |||
|
| Device |
|
| Express ports |
|
|
| Device |
|
|
|
|
|
|
| (Device 1 and |
|
|
| (Device 0) |
|
|
|
|
|
|
| Device 6) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||
|
|
|
|
|
| DMI |
| ||||
|
|
|
|
|
|
|
|
|
|
|
|
PCI Express* extends the configuration space to 4096 bytes
The PCI Express* Host Bridge is required to translate the
PCI Express* Port
The PCI Express* interface on the processor is a single,
PCI Express* Lanes Connection
The following figure demonstrates the PCIe* lane mapping.
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
December 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 25 |