Power
•Reduced possible overshoot/undershoot signal quality issues seen by the processor I/O buffer receivers caused by reflections from potentially un- terminated transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are not driven.
At reset, all rows must be assumed to be populated, until it can be determined that the rows are not populated. This is due to the fact that when CKE is
CKE tristate should be enabled by BIOS where appropriate, since at reset all rows must be assumed to be populated.
4.3.2DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals, which the SDRAM controller supports. The processor drives four CKE pins to perform these operations.
The CKE is one of the
The processor supports three different types of
•No power-down (CKE disable)
•Active
•
The CKE is determined per rank, whenever it is inactive. Each rank has an idle- counter. The
It is important to understand that since the
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
December 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 61 |