![Digital Display Interface Group DC Specifications](/images/new-backgrounds/103135/103135201x1.webp)
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| Parameter | Min | Typ | Max | Units | Notes1 | |
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| DDR3/DDR3L Control |
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| 5, 11, |
| RON_DN(CTL) |
| Buffer | 19 | 25 | 31 | Ω | ||
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| Resistance |
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| DDR3/DDR3L Reset |
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| RON_UP(RST) |
| Buffer | 40 | 80 | 130 | Ω | — | |
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| Resistance |
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| DDR3/DDR3L Reset |
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| RON_DN(RST) |
| Buffer | 40 | 80 | 130 | Ω | — | |
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| Resistance |
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| Input Leakage Current |
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| (DQ, CK) |
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| ILI |
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| 0V | — | — | 0.7 | mA | — |
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| 0.2*VDDQ |
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| 0.8*VDDQ |
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| Input Leakage Current |
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| (CMD, CTL) |
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| ILI |
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| 0V | — | — | 1.0 | mA | — |
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| 0.2*VDDQ |
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| 0.8*VDDQ |
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| SM_RCOMP0 |
| Command COMP | 99 | 100 | 101 | Ω | 8 | |
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| SM_RCOMP1 |
| Data COMP Resistance | 74.25 | 75 | 75.75 | Ω | 8 | |
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| SM_RCOMP2 |
| ODT COMP Resistance | 99 | 100 | 101 | Ω | 8 | |
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| Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. |
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| 2. | VIL | is defined as the maximum voltage level at a receiving agent that will be interpreted as a | ||||||
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| logical low value. |
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| 3. | VIH | is defined as the minimum voltage level at a receiving agent that will be interpreted as a | ||||||
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| logical high value. |
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| 4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply | ||||||||
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| with the signal quality specifications. |
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| 5. This is the pull up/down driver resistance. |
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| 6. RTERM is the termination on the DIMM and in not controlled by the processor. |
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| 7. The minimum and maximum values for these signals are programmable by BIOS to one of the | ||||||||
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| two sets. |
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| 8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx | ||||||||
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| resistors are to VSS. |
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| 9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ | ||||||||
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| *0.47. |
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| 10.SM_VREF is defined as VDDQ/2. |
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| boot training. |
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| 12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods. |
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| 13.The MRC during boot training might optimize RON outside the range specified. |
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Table 51. | Digital Display Interface Group DC Specifications |
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| Symbol | Parameter | Min | Typ | Max | Units |
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| VIL | HPD Input Low Voltage | — | — | 0.8 | V |
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| VIH | HPD Input High Voltage | 2.25 | — | 3.6 | V |
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| Vaux(Tx) | Aux | 0.39 | — | 1.38 | V |
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| Vaux(Rx) | Aux | 0.32 | — | 1.36 | V |
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Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
December 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 101 |