PCI Express* DC Specifications

Electrical Specifications—Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

Max

Units

Notes1

 

VIH

 

Input High Voltage (other GTL)

VCCIO_TERM * 0.72

V

2, 4

 

 

 

 

 

 

 

 

 

RON

 

Buffer on Resistance (CFG/BPM)

16

24

Ω

 

 

 

 

 

 

 

 

 

RON

 

Buffer on Resistance (other GTL)

12

28

Ω

 

 

 

 

 

 

 

 

 

ILI

 

Input Leakage Current

±150

μA

3

 

 

 

 

 

 

 

 

 

Notes: 1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

 

 

2.

The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.

 

 

3.

For VIN between 0 V and VCCIO_TERM. Measured when the driver is tri-stated.

 

 

 

4.

VIH and VOH may experience excursions above VCCIO_TERM. However, input signal drivers must

 

 

comply with the signal quality specifications.

 

 

 

 

 

 

 

 

 

 

 

Table 55.

PCI Express* DC Specifications

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

 

Typ

Max

Units

 

Notes1

 

ZTX-DIFF-DC

 

DC Differential Tx Impedance (Gen 1

80

 

120

Ω

 

1, 6

 

 

Only)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZTX-DIFF-DC

 

DC Differential Tx Impedance (Gen 2 and

 

120

Ω

 

1, 6

 

 

Gen 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZRX-DC

 

DC Common Mode Rx Impedance

40

 

60

Ω

 

1, 4, 5

 

 

 

 

 

 

 

 

 

 

 

 

ZRX-DIFF-DC

 

DC Differential Rx Impedance (Gen1

80

 

120

Ω

 

1

 

 

Only)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PEG_RCOMP

Comp Resistance

24.75

 

25

25.25

Ω

 

2, 3

 

 

 

 

 

 

 

 

 

 

 

 

Notes: 1.

See the PCI Express Base Specification for more details.

 

 

 

 

 

 

2.

PEG_RCOMP should be connected to VCOMP_OUT through a 25 Ω ±1% resistor.

 

 

 

 

3.

Intel allows using 24.9 Ω ±1% resistors.

 

 

 

 

 

 

 

 

4.

DC impedance limits are needed to ensure Receiver detect.

 

 

 

 

 

 

5.

The Rx DC Common Mode Impedance must be present when the Receiver terminations are first

 

 

enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can

 

 

start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω

 

 

±20%) must be within the specified range by the time Detect is entered.

 

 

 

 

6.

Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.

 

 

 

 

 

 

 

 

 

 

 

 

7.8.1Platform Environment Control Interface (PECI) DC Characteristics

The PECI interface operates at a nominal voltage set by VCCIO_TERM. The set of DC electrical specifications shown in the following table is used with devices normally operating from a VCCIO_TERM interface supply.

VCCIO_TERM nominal levels will vary between processor families. All PECI devices will operate at the VCCIO_TERM level determined by the processor installed in the system.

Table 56. Platform Environment Control Interface (PECI) DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

 

Notes1

Rup

Internal pull up resistance

15

45

Ω

 

3

 

 

 

 

 

 

 

Vin

Input Voltage Range

-0.15

VCCIO_TERM +

V

 

 

0.15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vhysteresis

Hysteresis

0.1 *

N/A

V

 

 

VCCIO_TERM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

continued...

Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013

Datasheet – Volume 1 of 2

Order No.: 328897-004

103

Page 103
Image 103
Intel BX80633I74960X manual Platform Environment Control Interface PECI DC Characteristics, PCI Express* DC Specifications

BX80633I74960X, BX80646I34130, BX80646I54430, BX80646I74770K, BX80646I74770 specifications

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