Intel BXF80646I74770K manual Memory Channel B Signals, Signal Description-Processor, continued

Signal Description—Processor
	Signal Name	Description	Direction / Buffer
			Type
	SA_RAS#	RAS Control Signal: This signal is used with SA_CAS# and	O
		SA_WE# (along with SA_CS#) to define the SRAM Commands.	DDR3/DDR3L
	SA_CAS#	CAS Control Signal: This signal is used with SA_RAS# and	O
		SA_WE# (along with SA_CS#) to define the SRAM Commands.	DDR3/DDR3L
		Data Strobes: SA_DQS[8:0] and its complement signal group	I/O
	SA_DQS[8:0]	make up a differential strobe pair. The data is captured at the
	SA_DQSN[8:0]	crossing point of SA_DQS[8:0] and SA_DQS#[8:0] during read	DDR3/DDR3L
		and write transactions.
	SA_DQ[63:0]	Data Bus: Channel A data signal interface to the SDRAM data	I/O
		bus.	DDR3/DDR3L
	SA_MA[15:0]	Memory Address: These signals are used to provide the	O
		multiplexed row and column address to the SDRAM.	DDR3/DDR3L
		SDRAM Differential Clock: These signals are Channel A
		SDRAM Differential clock signal pairs. The crossing of the	O
	SA_CK[3:0]	positive edge of SA_CK and the negative edge of its complement
			DDR3/DDR3L
		SA_CK# are used to sample the command and control signals on
		the SDRAM.
		Clock Enable: (1 per rank). These signals are used to:
	SA_CKE[3:0]	• Initialize the SDRAMs during power-up	O
		• Power-down SDRAM ranks	DDR3/DDR3L
		• Place all SDRAM ranks into and out of self-refresh during STR
		Chip Select: (1 per rank). These signals are used to select	O
	SA_CS#[3:0]	particular SDRAM components during the active state. There is
			DDR3/DDR3L
		one Chip Select for each SDRAM rank.
	SA_ODT[3:0]	On Die Termination: Active Termination Control.	O
			DDR3/DDR3L
Table 31.	Memory Channel B Signals
	Signal Name	Description	Direction / Buffer
			Type
	SB_BS[2:0]	Bank Select: These signals define which banks are selected	O
		within each SDRAM rank.	DDR3/DDR3L
		Write Enable Control Signal: This signal is used with	O
	SB_WE#	SB_RAS# and SB_CAS# (along with SB_CS#) to define the
			DDR3/DDR3L
		SDRAM Commands.
	SB_RAS#	RAS Control Signal: This signal is used with SB_CAS# and	O
		SB_WE# (along with SB_CS#) to define the SRAM Commands.	DDR3/DDR3L
	SB_CAS#	CAS Control Signal: This signal is used with SB_RAS# and	O
		SB_WE# (along with SB_CS#) to define the SRAM Commands.	DDR3/DDR3L
		Data Strobes: SB_DQS[8:0] and its complement signal group	I/O
	SB_DQS[8:0]	make up a differential strobe pair. The data is captured at the
	SB_DQSN[8:0]	crossing point of SB_DQS[8:0] and its SB_DQS#[8:0] during	DDR3/DDR3L
		read and write transactions.
	SB_DQ[63:0]	Data Bus: Channel B data signal interface to the SDRAM data	I/O
		bus.	DDR3/DDR3L
	SB_MA[15:0]	Memory Address: These signals are used to provide the	O
		multiplexed row and column address to the SDRAM.	DDR3/DDR3L
			continued...

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	83