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Intel BX80646I74770S Thermal Metrology, Fan Speed Control Scheme with Digital Thermal Sensor DTS

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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5.2Thermal Metrology

Thermal Management—Processor

5.2Thermal Metrology

The maximum Thermal Test Vehicle (TTV) case temperatures (TCASE-MAX) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter. The TTV TCASE is measured at the geometric top center of the TTV integrated heat spreader (IHS). The following figure illustrates the location where TCASE temperature measurements should be made.

Figure 19. Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location

Measure TCASE at

the geometric center of the package

37.5

37.5

Note: THERM-X OF CALIFORNIA can machine the groove and attach a thermocouple to the IHS. The supplier is subject to change without notice. THERM-X OF CALIFORNIA, 1837 Whipple Road, Hayward, Ca 94544. Ernesto B Valencia +1-510-441-7566 Ext. 242 ernestov@therm-x.com. The vendor part number is XTMS1565.

5.3Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1

To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT, and ensure that the Fan Speed Control (FSC) can provide a ΨCA that is equivalent or greater than the ΨCA specification.

The DTS 1.1 implementation consists of two points: a ΨCA at TCONTROL and a ΨCA at DTS = -1.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	71

Image 71

Intel BX80646I74770S, BX80646I54430 Thermal Metrology, Fan Speed Control Scheme with Digital Thermal Sensor DTS, 37.5 37.5

Contents

December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 1.0 Introduction Contents4.0 Power Management Revision History5.0 Thermal Management 6.0 Signal DescriptionProcessor-Contents 7.8.1 Platform Environment Control Interface PECI DC Characteristics 7.0 Electrical Specifications8.0 Package Mechanical Specifications 9.0 Processor Ball and Signal InformationFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 IntroductionPlatform Controller Hub PCH Figure 1. Platform Block Diagram1.1 Supported Technologies ProcessorSystem 1.3 Power Management Support1.2 Interfaces Processor CoreTerminology 1.4 Thermal Management Support1.5 Package Support 1.6 Terminologycontinued with Virtual Machine Monitor software, enables multiple, robust independent softwareProcessor-Introduction continued Introduction-ProcessorTerm DescriptionDocument 1.7 Related DocumentsRelated Documents Processor-IntroductionDocument specificationsIntroduction-Processor Document2.1 System Memory Interface 2.0 InterfacesProcessor DIMM Support by Product Supported UDIMM Module Configurations2.1.1 System Memory Technology Supported DDR3 / DDR3L System Memory Timing Support Supported SO-DIMM Module Configurations AIO Only2.1.2 System Memory Timing Support 2.1.3 System Memory Organization Modes Single-Channel ModeDual-Channel Mode - Intel Flex Memory Technology Mode Dual-Channel Symmetric Mode2.1.3.1 System Memory Frequency 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsJust-in-Time Command Scheduling Command Overlap2.1.3.3 Data Scrambling Table 7. PCI Express* Supported Configurations in Desktop Products2.2 PCI Express* Interface 2.2.1 PCI Express* Support2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Lanes Connection PCI Express* Related Register Structures in the ProcessorPCI Express* Port 1 X 8 Controller 2.3 Direct Media Interface DMIFigure 4. PCI Express* Typical Operation 16 Lanes Mapping 1 X 4 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics3D Engine Execution Units Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics Processing 3D PipelineStrips and Fans SF Stage Vertex Shader VS StageGeometry Shader GS Stage Clip StageLogical 128-Bit Fixed BLT and 256 Fill Engine 2.6 Digital Display Interface DDI2.5.2 Multi Graphics Controllers Multi-Monitor Support Figure 6. Processor Display Architecture Figure 7. DisplayPort* Overview Source DeviceSink Device DisplayPortHDMI Tx HDMI SourceHDMI Sink Figure 8. HDMI* OverviewTable 8. Processor Supported Audio Formats over HDMI*and DisplayPort Multiple Display Configurationsembedded DisplayPort Integrated AudioHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.8.1 PECI Bus Architecture 2.7 Intel Flexible Display Interface Intel FDI2.8 Platform Environmental Control Interface PECI PECI Client Figure 9. PECI Host-Clients Connection ExamplePECI Host / Originatoring=VT 3.0 Technologies3.1 Intel Virtualization Technology Intel VT Intel VT-x ObjectivesIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology Intel Turbo Boost Technology 2.0 Frequency 3.4 Intel Turbo Boost Technology3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 Intel Secure Key 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIPCLMULQDQ Instruction 3.8 Intel 64 Architecture x2APIC 3.11 Supervisor Mode Execution Protection SMEP 3.9 Power Aware Interrupt Routing PAIR3.10 Execute Disable Bit S0 - Processor Fully powered on full on mode / connected standby mode 4.0 Power ManagementFigure 11. Processor Power States Note Power states availability may vary between the different SKUsIntegrated Memory Controller States 4.1 Advanced Configuration and Power Interface ACPI States SupportedSystem States Processor Core / Package State SupportG, S, and C Interface State Combinations 4.2 Processor Core Power Management4.2.1 Enhanced Intel SpeedStep Technology Key Features Direct Media Interface DMI StatesThread 4.2.2 Low-Power Idle StatesFigure 12. Idle Power Management Breakdown of the Processor Cores ThreadFigure 13. Thread and Core C-State Entry and Exit 4.2.3 Requesting Low-Power Idle StatesCoordination of Thread Power States at the Core Level Core C3 State 4.2.4 Core C-State RulesCore C0 State Core C1/C1E StateC-State Auto-Demotion 4.2.5 Package C-StatesCore C6 State Core C7 StateCoordination of Core Power States at the Package Level Package C1/C1E State Figure 14. Package C-State Entry and ExitPackage C0 State Package C7 State Package C2 StatePackage C3 State Package C6 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power-Down4.3.2.1 Initialization Role of CKE 4.3.4 DDR Electrical Power Gating EPG 4.4 PCI Express* Power Management4.5 Direct Media Interface DMI Power Management 4.3.3 DRAM Running Average Power Limitation RAPL4.6.3 Intel Graphics Dynamic Frequency 4.6 Graphics Power Management4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6.2 Graphics Render C-StateThermal Management-Processor 5.0 Thermal ManagementProcessor-Thermal Management Desktop Processor Thermal Specifications5.1 Desktop Processor Thermal Profiles Temperature on pageCase 5.1.1 Processor PCG 2013D Thermal ProfileTCASE = 0.33 * Power + TTV Power Wcontinued 5.1.2 Processor PCG 2013C Thermal ProfileProcessor-Thermal Management continuedcontinued 5.1.3 Processor PCG 2013B Thermal ProfileThermal Management-Processor Processor-Thermal Management 5.1.4 Processor PCG 2013A Thermal Profile37.5 37.5 5.2 Thermal Metrology5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS Measure TCASE at the geometric center of the packageΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Thermal Margin Slope 5.5 Processor TemperatureFigure 21. Digital Thermal Sensor DTS Thermal Profile Definition Frequency Control 5.6 Adaptive Thermal MonitorImmediate Transition to Combined TM1 and TM2 Critical Temperature FlagClock Modulation PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.9 Intel Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power ControlMemory Channel A Signals 6.0 Signal Description6.1 System Memory Interface Signals Signal Description Buffer Typescontinued Memory Channel B SignalsSignal Description-Processor Write Enable Control Signal This signal is used withDDR3/DDR3L Reference Voltage This signal is used as 6.2 Memory Reference and Compensation SignalsMemory Reference and Compensation Signals Processor-Signal DescriptionCFG3 MSR Privacy Bit Feature 6.3 Reset and Miscellaneous SignalsReset and Miscellaneous Signals Signal Description-ProcessorDisplay Interface Signals 6.4 PCI Express*-Based Interface Signals6.5 Display Interface Signals PCI Express* Graphics Interface SignalsTestability Signals 6.7 Phase Locked Loop PLL Signals6.8 Testability Signals Phase Locked Loop PLL SignalsPower Sequencing Signals 6.9 Error and Thermal Protection Signals6.10 Power Sequencing Signals Error and Thermal Protection SignalsProcessor Power Signals 6.11 Processor Power Signals6.12 Sense Signals 6.13 Ground and Non-Critical to Function NCTF Signals7.3 VCC Voltage Identification VID 7.0 Electrical Specifications7.2 Power and Ground Lands 7.1 Integrated Voltage Regulatorcontinued Table 45. Voltage Regulator VR 12.5 Voltage IdentificationElectrical Specifications-Processor continuedcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued continued Processor-Electrical SpecificationsSignal Groups 7.4 Reserved or Unused Signals7.5 Signal Groups DDR3 / DDR3L Compensation DDR3 / DDR3L Data SignalsDDR3 / DDR3L Reference Voltage Signals Power / Ground / OtherDigital Media Interface DMI 7.6 Test Access Port TAP Connection7.7 DC Specifications PCI Express* Graphicscontinued 7.8 Voltage and Current SpecificationsProcessor-Electrical Specifications Electrical Specifications-Processor continued DDR3 / DDR3L Signal Group DC SpecificationsVCCIOOUT, VCOMPOUT, and VCCIOTERM Processor-Electrical SpecificationsElectrical Specifications-Processor Digital Display Interface Group DC SpecificationsProcessor-Electrical Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications GTL Signal Group and Open Drain Signal Group DC Specificationscontinued 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsPCI Express* DC Specifications Electrical Specifications-ProcessorProcessor-Electrical Specifications 7.8.2 Input Device HysteresisFigure 23. Input Device Hysteresis 8.1 Processor Component Keep-Out Zone 8.0 Package Mechanical Specifications8.2 Package Loading Specifications Figure 24. Processor Package Assembly Sketch8.3 Package Handling Guidelines 8.4 Package Insertion Specifications8.5 Processor Mass Specification Processor Loading SpecificationsFigure 25. Processor Top-Side Markings 8.7 Processor Markings8.8 Processor Land Coordinates Processor MaterialsProcessor-Package Mechanical Specifications 8.9 Processor Storage SpecificationsProcessor Storage Specifications Figure 26. Processor Package Land CoordinatesTIMEsustained storage Package Mechanical Specifications-ProcessorRHsustained storage Processor Ball List by Signal Name 9.0 Processor Ball and Signal Informationcontinued Processor Ball and Signal Information-Processorcontinued continuedcontinued Processor-Processor Ball and Signal Informationcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameAU20 continuedcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal Name