Intel BX80646I74770K, CM8064601466200 manual Phase Locked Loop PLL Signals, Testability Signals

Signal Description—Processor

6.7Phase Locked Loop (PLL) Signals

Table 37.	Phase Locked Loop (PLL) Signals
	Signal Name	Description	Direction / Buffer
			Type
	BCLKP	Differential bus clock input to the processor	I
	BCLKN		Diff Clk
	DPLL_REF_CLKP	Embedded Display Port PLL Differential Clock In:	I
	DPLL_REF_CLKN	135 MHz	Diff Clk
	SSC_DPLL_REF_CLKP	Spread Spectrum Embedded DisplayPort PLL	I
	SSC_ DPLL_REF_CLKN	Differential Clock In: 135 MHz	Diff Clk

6.8Testability Signals

Table 38.	Testability Signals
	Signal Name	Description	Direction / Buffer
			Type
		Breakpoint and Performance Monitor Signals:	I/O
	BPM#[7:0]	Outputs from the processor that indicate the status of
		breakpoints and programmable counters used for	CMOS
		monitoring processor performance.
		Debug Reset: This signal is used only in systems where
	DBR#	no debug port is implemented on the system board.	O
		DBR# is used by a debug port interposer so that an in-
		target probe can drive system reset.
		Processor Ready: This signal is a processor output	O
	PRDY#	used by debug tools to determine processor debug
			Asynchronous CMOS
		readiness.
	PREQ#	Processor Request: This signal is used by debug tools	I
		to request debug operation of the processor.	Asynchronous CMOS
		Test Clock: This signal provides the clock input for the	I
	TCK	processor Test Bus (also known as the Test Access
		Port). This signal must be driven low or allowed to float	GTL
		during power on Reset.
		Test Data In: This signal transfers serial test data into	I
	TDI	the processor. This signal provides the serial input
			GTL
		needed for JTAG specification support.
		Test Data Out: This signal transfers serial test data out	O
	TDO	of the processor. This signal provides the serial output
			Open Drain
		needed for JTAG specification support.
	TMS	Test Mode Select: This is a JTAG specification	I
		supported signal used by debug tools.	GTL
		Test Reset: This signal resets the Test Access Port	I
	TRST#	(TAP) logic. This signal must be driven low during power
			GTL
		on Reset.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	87