Intel BX80637I73770K, CM8064601466200 manual Introduction-Processor, Term, Description, continued

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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Introduction—Processor

Term

Description

 

 

MLC

Mid-Level Cache

 

 

MSI

Message Signaled Interrupt

 

 

MSL

Moisture Sensitive Labeling

 

 

MSR

Model Specific Registers

 

 

 

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical

NCTF

reserved, so the loss of the solder joint continuity at end of life conditions will not

 

affect the overall product functionality.

 

 

ODT

On-Die Termination

 

 

OLTM

Open Loop Thermal Management

 

 

PCG

Platform Compatibility Guide (PCG) (previously known as FMB) provides a design

target for meeting all planned processor frequency requirements.

 

 

 

 

Platform Controller Hub. The chipset with centralized platform capabilities including

PCH

the main I/O interfaces along with display connectivity, audio features, power

 

management, manageability, security, and storage features.

 

 

 

The Platform Environment Control Interface (PECI) is a one-wire interface that

PECI

provides a communication channel between Intel processor and chipset components

 

to external monitoring devices.

 

 

 

Case-to-ambient thermal characterization parameter (psi). A measure of thermal

Ψ ca

solution performance using total package power. Defined as (TCASE - TLA ) / Total

 

Package Power. The heat source should always be specified for Y measurements.

 

 

 

PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a

PEG

high-speed serial interface where configuration is software compatible with the

 

existing PCI specifications.

 

 

PL1, PL2

Power Limit 1 and Power Limit 2

 

 

PPD

Pre-charge Power-down

 

 

Processor

The 64-bit multi-core component (package)

 

 

 

The term “processor core” refers to Si die itself, which can contain multiple execution

Processor Core

cores. Each execution core has an instruction cache, data cache, and 256-KB L2

 

cache. All execution cores share the L3 cache.

 

 

Processor Graphics

Intel Processor Graphics

 

 

Rank

A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These

devices are usually, but not always, mounted on a single side of a SO-DIMM.

 

 

 

SCI

System Control Interrupt. SCI is used in the ACPI protocol.

 

 

SF

Strips and Fans

 

 

SMM

System Management Mode

 

 

SMX

Safer Mode Extensions

 

 

 

A non-operational state. The processor may be installed in a platform, in a tray, or

 

loose. Processors may be sealed in packaging or exposed to free air. Under these

 

conditions, processor landings should not be connected to any supply voltages, have

Storage Conditions

any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed

 

packaging or a device removed from packaging material), the processor must be

 

handled in accordance with moisture sensitivity labeling (MSL) as indicated on the

 

packaging material.

 

 

SVID

Serial Voltage Identification

 

 

TAC

Thermal Averaging Constant

 

 

 

continued...

Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013

Datasheet – Volume 1 of 2

Order No.: 328897-004

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Intel BX80637I73770K, CM8064601466200, CM8064601466003, CM8063701212200 Introduction-Processor, Term, Description, continued