Term | Description | |
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MLC | ||
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MSI | Message Signaled Interrupt | |
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MSL | Moisture Sensitive Labeling | |
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MSR | Model Specific Registers | |
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NCTF | reserved, so the loss of the solder joint continuity at end of life conditions will not | |
| affect the overall product functionality. | |
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ODT | ||
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OLTM | Open Loop Thermal Management | |
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PCG | Platform Compatibility Guide (PCG) (previously known as FMB) provides a design | |
target for meeting all planned processor frequency requirements. | ||
| ||
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| Platform Controller Hub. The chipset with centralized platform capabilities including | |
PCH | the main I/O interfaces along with display connectivity, audio features, power | |
| management, manageability, security, and storage features. | |
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| The Platform Environment Control Interface (PECI) is a | |
PECI | provides a communication channel between Intel processor and chipset components | |
| to external monitoring devices. | |
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Ψ ca | solution performance using total package power. Defined as (TCASE - TLA ) / Total | |
| Package Power. The heat source should always be specified for Y measurements. | |
|
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| PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a | |
PEG | ||
| existing PCI specifications. | |
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PL1, PL2 | Power Limit 1 and Power Limit 2 | |
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PPD | ||
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Processor | The | |
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| The term “processor core” refers to Si die itself, which can contain multiple execution | |
Processor Core | cores. Each execution core has an instruction cache, data cache, and | |
| cache. All execution cores share the L3 cache. | |
|
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Processor Graphics | Intel Processor Graphics | |
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Rank | A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These | |
devices are usually, but not always, mounted on a single side of a | ||
| ||
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SCI | System Control Interrupt. SCI is used in the ACPI protocol. | |
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SF | Strips and Fans | |
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SMM | System Management Mode | |
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SMX | Safer Mode Extensions | |
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| A | |
| loose. Processors may be sealed in packaging or exposed to free air. Under these | |
| conditions, processor landings should not be connected to any supply voltages, have | |
Storage Conditions | any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed | |
| packaging or a device removed from packaging material), the processor must be | |
| handled in accordance with moisture sensitivity labeling (MSL) as indicated on the | |
| packaging material. | |
|
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SVID | Serial Voltage Identification | |
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TAC | Thermal Averaging Constant | |
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| continued... |
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
December 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 15 |