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Intel BX80646I34130, CM8064601466200, CM8064601466003, BX80646I74770 Signal Name, Ball #, continued

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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Processor Ball and Signal Information—Processor

	Signal Name	Ball #		Signal Name	Ball #		Signal Name	Ball #

	VCC	A24		VCC	E29		VCC	J22

	VCC	A25		VCC	E30		VCC	J23

	VCC	A26		VCC	E31		VCC	J24

	VCC	A27		VCC	E32		VCC	J25

	VCC	A28		VCC	E33		VCC	J26

	VCC	A29		VCC	E34		VCC	J27

	VCC	A30		VCC	E35		VCC	J28

	VCC	B25		VCC	F23		VCC	J29

	VCC	B27		VCC	F25		VCC	J30

	VCC	B29		VCC	F27		VCC	J31

	VCC	B31		VCC	F29		VCC	J32

	VCC	B33		VCC	F31		VCC	J33

	VCC	B35		VCC	F33		VCC	J34

	VCC	C24		VCC	F35		VCC	J35

	VCC	C25		VCC	G22		VCC	K19

	VCC	C26		VCC	G23		VCC	K21

	VCC	C27		VCC	G24		VCC	K23

	VCC	C28		VCC	G25		VCC	K25

	VCC	C29		VCC	G26		VCC	K27

	VCC	C30		VCC	G27		VCC	K29

	VCC	C31		VCC	G28		VCC	K31

	VCC	C32		VCC	G29		VCC	K33

	VCC	C33		VCC	G30		VCC	K35

	VCC	C34		VCC	G31		VCC	L15

	VCC	C35		VCC	G32		VCC	L16

	VCC	D25		VCC	G33		VCC	L17

	VCC	D27		VCC	G34		VCC	L18

	VCC	D29		VCC	G35		VCC	L19

	VCC	D31		VCC	H23		VCC	L20

	VCC	D33		VCC	H25		VCC	L21

	VCC	D35		VCC	H27		VCC	L22

	VCC	E24		VCC	H29		VCC	L23

	VCC	E25		VCC	H31		VCC	L24

	VCC	E26		VCC	H33		VCC	L25

	VCC	E27		VCC	H35		VCC	L26

	VCC	E28		VCC	J21		VCC	L27

		continued...			continued...			continued...

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	115

Image 115

Intel BX80646I34130, CM8064601466200, CM8064601466003, BX80637I73770K, CM8063701212200 manual Signal Name, Ball #, continued

Contents

December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 1.0 Introduction Contents4.0 Power Management Revision HistoryProcessor-Contents 6.0 Signal Description5.0 Thermal Management 7.8.1 Platform Environment Control Interface PECI DC Characteristics 7.0 Electrical Specifications8.0 Package Mechanical Specifications 9.0 Processor Ball and Signal InformationFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 IntroductionPlatform Controller Hub PCH Figure 1. Platform Block Diagram1.1 Supported Technologies ProcessorSystem 1.3 Power Management Support1.2 Interfaces Processor CoreTerminology 1.4 Thermal Management Support1.5 Package Support 1.6 TerminologyProcessor-Introduction with Virtual Machine Monitor software, enables multiple, robust independent softwarecontinued continued Introduction-ProcessorTerm DescriptionDocument 1.7 Related DocumentsRelated Documents Processor-IntroductionDocument specificationsIntroduction-Processor Document2.1 System Memory Interface 2.0 Interfaces2.1.1 System Memory Technology Supported Supported UDIMM Module ConfigurationsProcessor DIMM Support by Product 2.1.2 System Memory Timing Support Supported SO-DIMM Module Configurations AIO OnlyDDR3 / DDR3L System Memory Timing Support 2.1.3 System Memory Organization Modes Single-Channel ModeDual-Channel Mode - Intel Flex Memory Technology Mode Dual-Channel Symmetric Mode2.1.3.1 System Memory Frequency 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsJust-in-Time Command Scheduling Command Overlap2.1.3.3 Data Scrambling Table 7. PCI Express* Supported Configurations in Desktop Products2.2 PCI Express* Interface 2.2.1 PCI Express* Support2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Port PCI Express* Related Register Structures in the ProcessorPCI Express* Lanes Connection 1 X 8 Controller 2.3 Direct Media Interface DMIFigure 4. PCI Express* Typical Operation 16 Lanes Mapping 1 X 4 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics3D Engine Execution Units Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics Processing 3D PipelineStrips and Fans SF Stage Vertex Shader VS StageGeometry Shader GS Stage Clip Stage2.5.2 Multi Graphics Controllers Multi-Monitor Support 2.6 Digital Display Interface DDILogical 128-Bit Fixed BLT and 256 Fill Engine Figure 6. Processor Display Architecture Figure 7. DisplayPort* Overview Source DeviceSink Device DisplayPortHDMI Tx HDMI SourceHDMI Sink Figure 8. HDMI* OverviewTable 8. Processor Supported Audio Formats over HDMI*and DisplayPort Multiple Display Configurationsembedded DisplayPort Integrated AudioHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.8 Platform Environmental Control Interface PECI 2.7 Intel Flexible Display Interface Intel FDI2.8.1 PECI Bus Architecture PECI Client Figure 9. PECI Host-Clients Connection ExamplePECI Host / Originatoring=VT 3.0 Technologies3.1 Intel Virtualization Technology Intel VT Intel VT-x ObjectivesIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology 3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 3.4 Intel Turbo Boost TechnologyIntel Turbo Boost Technology 2.0 Frequency PCLMULQDQ Instruction 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIIntel Secure Key 3.8 Intel 64 Architecture x2APIC 3.10 Execute Disable Bit 3.9 Power Aware Interrupt Routing PAIR3.11 Supervisor Mode Execution Protection SMEP S0 - Processor Fully powered on full on mode / connected standby mode 4.0 Power ManagementFigure 11. Processor Power States Note Power states availability may vary between the different SKUsIntegrated Memory Controller States 4.1 Advanced Configuration and Power Interface ACPI States SupportedSystem States Processor Core / Package State SupportG, S, and C Interface State Combinations 4.2 Processor Core Power Management4.2.1 Enhanced Intel SpeedStep Technology Key Features Direct Media Interface DMI StatesThread 4.2.2 Low-Power Idle StatesFigure 12. Idle Power Management Breakdown of the Processor Cores ThreadCoordination of Thread Power States at the Core Level 4.2.3 Requesting Low-Power Idle StatesFigure 13. Thread and Core C-State Entry and Exit Core C3 State 4.2.4 Core C-State RulesCore C0 State Core C1/C1E StateC-State Auto-Demotion 4.2.5 Package C-StatesCore C6 State Core C7 StateCoordination of Core Power States at the Package Level Package C0 State Figure 14. Package C-State Entry and ExitPackage C1/C1E State Package C7 State Package C2 StatePackage C3 State Package C6 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.1 Initialization Role of CKE 4.3.2.3 Dynamic Power-Down4.3.2.2 Conditional Self-Refresh 4.3.4 DDR Electrical Power Gating EPG 4.4 PCI Express* Power Management4.5 Direct Media Interface DMI Power Management 4.3.3 DRAM Running Average Power Limitation RAPL4.6.3 Intel Graphics Dynamic Frequency 4.6 Graphics Power Management4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6.2 Graphics Render C-StateThermal Management-Processor 5.0 Thermal ManagementProcessor-Thermal Management Desktop Processor Thermal Specifications5.1 Desktop Processor Thermal Profiles Temperature on pageCase 5.1.1 Processor PCG 2013D Thermal ProfileTCASE = 0.33 * Power + TTV Power Wcontinued 5.1.2 Processor PCG 2013C Thermal ProfileProcessor-Thermal Management continuedThermal Management-Processor 5.1.3 Processor PCG 2013B Thermal Profilecontinued Processor-Thermal Management 5.1.4 Processor PCG 2013A Thermal Profile37.5 37.5 5.2 Thermal Metrology5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS Measure TCASE at the geometric center of the packageΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Figure 21. Digital Thermal Sensor DTS Thermal Profile Definition 5.5 Processor TemperatureThermal Margin Slope Frequency Control 5.6 Adaptive Thermal MonitorClock Modulation Critical Temperature FlagImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.9 Intel Turbo Boost Technology Thermal Considerations 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.8.1 Digital Thermal Sensor Accuracy Taccuracy Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power ControlMemory Channel A Signals 6.0 Signal Description6.1 System Memory Interface Signals Signal Description Buffer Typescontinued Memory Channel B SignalsSignal Description-Processor Write Enable Control Signal This signal is used withDDR3/DDR3L Reference Voltage This signal is used as 6.2 Memory Reference and Compensation SignalsMemory Reference and Compensation Signals Processor-Signal DescriptionCFG3 MSR Privacy Bit Feature 6.3 Reset and Miscellaneous SignalsReset and Miscellaneous Signals Signal Description-ProcessorDisplay Interface Signals 6.4 PCI Express*-Based Interface Signals6.5 Display Interface Signals PCI Express* Graphics Interface SignalsTestability Signals 6.7 Phase Locked Loop PLL Signals6.8 Testability Signals Phase Locked Loop PLL SignalsPower Sequencing Signals 6.9 Error and Thermal Protection Signals6.10 Power Sequencing Signals Error and Thermal Protection SignalsProcessor Power Signals 6.11 Processor Power Signals6.12 Sense Signals 6.13 Ground and Non-Critical to Function NCTF Signals7.3 VCC Voltage Identification VID 7.0 Electrical Specifications7.2 Power and Ground Lands 7.1 Integrated Voltage Regulatorcontinued Table 45. Voltage Regulator VR 12.5 Voltage IdentificationElectrical Specifications-Processor continuedcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued continued Processor-Electrical Specifications7.5 Signal Groups 7.4 Reserved or Unused SignalsSignal Groups DDR3 / DDR3L Compensation DDR3 / DDR3L Data SignalsDDR3 / DDR3L Reference Voltage Signals Power / Ground / OtherDigital Media Interface DMI 7.6 Test Access Port TAP Connection7.7 DC Specifications PCI Express* GraphicsProcessor-Electrical Specifications 7.8 Voltage and Current Specificationscontinued Electrical Specifications-Processor continued DDR3 / DDR3L Signal Group DC SpecificationsVCCIOOUT, VCOMPOUT, and VCCIOTERM Processor-Electrical SpecificationsElectrical Specifications-Processor Digital Display Interface Group DC SpecificationsProcessor-Electrical Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications GTL Signal Group and Open Drain Signal Group DC Specificationscontinued 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsPCI Express* DC Specifications Electrical Specifications-ProcessorFigure 23. Input Device Hysteresis 7.8.2 Input Device HysteresisProcessor-Electrical Specifications 8.1 Processor Component Keep-Out Zone 8.0 Package Mechanical Specifications8.2 Package Loading Specifications Figure 24. Processor Package Assembly Sketch8.3 Package Handling Guidelines 8.4 Package Insertion Specifications8.5 Processor Mass Specification Processor Loading SpecificationsFigure 25. Processor Top-Side Markings 8.7 Processor Markings8.8 Processor Land Coordinates Processor MaterialsProcessor-Package Mechanical Specifications 8.9 Processor Storage SpecificationsProcessor Storage Specifications Figure 26. Processor Package Land CoordinatesRHsustained storage Package Mechanical Specifications-ProcessorTIMEsustained storage Processor Ball List by Signal Name 9.0 Processor Ball and Signal Informationcontinued Processor Ball and Signal Information-Processorcontinued continuedcontinued Processor-Processor Ball and Signal Informationcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameAU20 continuedcontinued continuedBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal Name