Package C2 State
Package C2 state is an internal processor state that cannot be explicitly requested by software. A processor enters Package C2 state when:
•All cores and graphics have requested a C3 or deeper power state; however, constraints (LTR, programmed timer events in the near future, and so on) prevent entry to any state deeper than C 2 state. Or,
•All cores and graphics are in the C3 or deeper power states, and a memory access request is received. Upon completion of all outstanding memory requests, the processor transitions back into a deeper package
Package C3 State
A processor enters the package C3
•At least one core is in the C3 state.
•The other cores are in a C3 state or deeper power state and the processor has been granted permission by the platform.
•The platform has not granted a request to a package C6 or deeper state, however, has allowed a package C6 state.
In package C3 state, the L3 shared cache is valid.
Package C6 State
A processor enters the package C6
•At least one core is in the C6 state.
•The other cores are in a C6 or deeper power state and the processor has been granted permission by the platform.
•If the cores are requesting C7 state, but the platform is limiting to a package C6 state, the last level cache in this case can be flushed.
In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts. It is possible the L3 shared cache is flushed and turned off in package C6 state. If at least one core is requesting C6 state, the L3 cache will not be flushed.
Package C7 State
The processor enters the package C7
Core break events are handled the same way as in package C3 or C6 state.
Note: C7 state may not be available on all SKUs.
Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family
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