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Intel BX80633I74960X Interfaces, Power Management Support, Processor Core, System, PCI Express

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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December 2013 Order No.: 328897-004

Processor—Introduction

•PCLMULQDQ Instruction

•Intel® Secure Key

•Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX- NI)

•PAIR – Power Aware Interrupt Routing

•SMEP – Supervisor Mode Execution Protection

Note: The availability of the features may vary between processor SKUs.

1.2Interfaces

The processor supports the following interfaces:

•DDR3/DDR3L

•Direct Media Interface (DMI)

•Digital Display Interface (DDI)

•PCI Express*

1.3Power Management Support

Processor Core

•Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C3, C6, C7

•Enhanced Intel SpeedStep® Technology

System

•S0, S3, S4, S5

Memory Controller

•Conditional self-refresh

•Dynamic power-down

PCI Express*

•L0s and L1 ASPM power management capability

DMI

•L0s and L1 ASPM power management capability

Processor Graphics Controller

•Intel® Rapid Memory Power Management (Intel® RMPM)

•Intel® Smart 2D Display Technology (Intel® S2DDT)

•Graphics Render C-state (RC6)

•Intel® Seamless Display Refresh Rate Switching with eDP port

•Intel® Display Power Saving Technology (Intel® DPST)

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 12

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Intel BX80633I74960X manual Interfaces, Power Management Support, Processor Core, System, Memory Controller, PCI Express

Contents

Datasheet - Volume 1 of DecemberDatasheet - Volume 1 of 2 Contents 4.0 Power ManagementRevision History 1.0 Introduction6.0 Signal Description Processor-Contents5.0 Thermal Management 7.0 Electrical Specifications 8.0 Package Mechanical Specifications9.0 Processor Ball and Signal Information 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables Tables-ProcessorProcessor-Tables Revision History Revision History-Processor1.0 Introduction Processor-IntroductionFigure 1. Platform Block Diagram 1.1 Supported TechnologiesProcessor Platform Controller Hub PCH1.3 Power Management Support 1.2 InterfacesProcessor Core System1.4 Thermal Management Support 1.5 Package Support1.6 Terminology Terminologywith Virtual Machine Monitor software, enables multiple, robust independent software Processor-Introductioncontinued Introduction-Processor TermDescription continued1.7 Related Documents Related DocumentsProcessor-Introduction Documentspecifications Introduction-ProcessorDocument Document2.0 Interfaces 2.1 System Memory InterfaceSupported UDIMM Module Configurations 2.1.1 System Memory Technology SupportedProcessor DIMM Support by Product Supported SO-DIMM Module Configurations AIO Only 2.1.2 System Memory Timing SupportDDR3 / DDR3L System Memory Timing Support 2.1.3 System Memory Organization Modes Single-Channel ModeDual-Channel Mode - Intel Flex Memory Technology Mode Figure 2. Intel Flex Memory Technology Operations2.1.3.2 Intel Fast Memory Access Intel FMA Technology Enhancements Just-in-Time Command SchedulingCommand Overlap 2.1.3.1 System Memory FrequencyTable 7. PCI Express* Supported Configurations in Desktop Products 2.2 PCI Express* Interface2.2.1 PCI Express* Support 2.1.3.3 Data Scrambling2.2.3 PCI Express* Configuration Mechanism 2.2.2 PCI Express* ArchitecturePCI Express* Related Register Structures in the Processor PCI Express* PortPCI Express* Lanes Connection 2.3 Direct Media Interface DMI Figure 4. PCI Express* Typical Operation 16 Lanes Mapping1 X 4 Controller 1 X 8 ControllerDMI Error Flow DMI Link Down2.4 Processor Graphics 2.5 Processor Graphics Controller GTFigure 5. Processor Graphics Controller Unit Block Diagram 2.5.1 3D and Video Engines for Graphics Processing3D Pipeline 3D Engine Execution UnitsVertex Shader VS Stage Geometry Shader GS StageClip Stage Strips and Fans SF Stage2.6 Digital Display Interface DDI 2.5.2 Multi Graphics Controllers Multi-Monitor SupportLogical 128-Bit Fixed BLT and 256 Fill Engine Figure 6. Processor Display Architecture Source Device Sink DeviceDisplayPort Figure 7. DisplayPort* OverviewHDMI Source HDMI SinkFigure 8. HDMI* Overview HDMI TxMultiple Display Configurations embedded DisplayPortIntegrated Audio Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortValid Three Display Configurations through the Processor High-bandwidth Digital Content Protection HDCP2.7 Intel Flexible Display Interface Intel FDI 2.8 Platform Environmental Control Interface PECI2.8.1 PECI Bus Architecture Figure 9. PECI Host-Clients Connection Example PECIHost / Originator PECI Client3.0 Technologies 3.1 Intel Virtualization Technology Intel VTIntel VT-x Objectives ing=VTIntel VT-x Features Intel VT-d Objectives Intel VT-d Features Figure 10. Device to Domain Mapping Structures3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology 3.4 Intel Turbo Boost Technology 3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2Intel Turbo Boost Technology 2.0 Frequency 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NI PCLMULQDQ InstructionIntel Secure Key 3.8 Intel 64 Architecture x2APIC 3.9 Power Aware Interrupt Routing PAIR 3.10 Execute Disable Bit3.11 Supervisor Mode Execution Protection SMEP 4.0 Power Management Figure 11. Processor Power StatesNote Power states availability may vary between the different SKUs S0 - Processor Fully powered on full on mode / connected standby mode4.1 Advanced Configuration and Power Interface ACPI States Supported System StatesProcessor Core / Package State Support Integrated Memory Controller States4.2 Processor Core Power Management 4.2.1 Enhanced Intel SpeedStep Technology Key FeaturesDirect Media Interface DMI States G, S, and C Interface State Combinations4.2.2 Low-Power Idle States Figure 12. Idle Power Management Breakdown of the Processor CoresThread Thread4.2.3 Requesting Low-Power Idle States Coordination of Thread Power States at the Core LevelFigure 13. Thread and Core C-State Entry and Exit 4.2.4 Core C-State Rules Core C0 StateCore C1/C1E State Core C3 State4.2.5 Package C-States Core C6 StateCore C7 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Figure 14. Package C-State Entry and Exit Package C0 StatePackage C1/C1E State Package C2 State Package C3 StatePackage C6 State Package C7 State4.2.6 Package C-States and Display Resolutions Deepest Package C-State Available4.3 Integrated Memory Controller IMC Power Management 4.3.1 Disabling Unused System Memory Outputs4.3.2 DRAM Power Management and Initialization No power-down CKE disable4.3.2.3 Dynamic Power-Down 4.3.2.1 Initialization Role of CKE4.3.2.2 Conditional Self-Refresh 4.4 PCI Express* Power Management 4.5 Direct Media Interface DMI Power Management4.3.3 DRAM Running Average Power Limitation RAPL 4.3.4 DDR Electrical Power Gating EPG4.6 Graphics Power Management 4.6.1 Intel Rapid Memory Power Management Intel RMPM4.6.2 Graphics Render C-State 4.6.3 Intel Graphics Dynamic Frequency5.0 Thermal Management Thermal Management-ProcessorDesktop Processor Thermal Specifications 5.1 Desktop Processor Thermal ProfilesProcessor-Thermal Management Profile5.1.1 Processor PCG 2013D Thermal Profile TCASE = 0.33 * Power +TTV Power W Case5.1.2 Processor PCG 2013C Thermal Profile Processor-Thermal Managementcontinued continued5.1.3 Processor PCG 2013B Thermal Profile Thermal Management-Processorcontinued 5.1.4 Processor PCG 2013A Thermal Profile Processor-Thermal Management5.2 Thermal Metrology 5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTSMeasure TCASE at the geometric center of the package 37.5 37.5Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS 5.5 Processor Temperature Figure 21. Digital Thermal Sensor DTS Thermal Profile DefinitionThermal Margin Slope 5.6 Adaptive Thermal Monitor Frequency ControlClock Modulation Immediate Transition to Combined TM1 and TM2Critical Temperature Flag PROCHOT# Signal 5.7 THERMTRIP# Signal 5.8 Digital Thermal Sensor5.9.1 Intel Turbo Boost Technology Power Control and Reporting 5.9 Intel Turbo Boost Technology Thermal Considerations5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.2 Package Power Control Intel Turbo Boost Technology 2.0 Package Power Control SettingsFigure 22. Package Power Control 5.9.3 Turbo Time Parameter6.0 Signal Description 6.1 System Memory Interface SignalsSignal Description Buffer Types Memory Channel A SignalsMemory Channel B Signals Signal Description-ProcessorWrite Enable Control Signal This signal is used with continued6.2 Memory Reference and Compensation Signals Memory Reference and Compensation SignalsProcessor-Signal Description DDR3/DDR3L Reference Voltage This signal is used as6.3 Reset and Miscellaneous Signals Reset and Miscellaneous SignalsSignal Description-Processor CFG3 MSR Privacy Bit Feature6.4 PCI Express*-Based Interface Signals 6.5 Display Interface SignalsPCI Express* Graphics Interface Signals Display Interface Signals6.7 Phase Locked Loop PLL Signals 6.8 Testability SignalsPhase Locked Loop PLL Signals Testability Signals6.9 Error and Thermal Protection Signals 6.10 Power Sequencing SignalsError and Thermal Protection Signals Power Sequencing Signals6.11 Processor Power Signals 6.12 Sense Signals6.13 Ground and Non-Critical to Function NCTF Signals Processor Power Signals7.0 Electrical Specifications 7.2 Power and Ground Lands7.1 Integrated Voltage Regulator 7.3 VCC Voltage Identification VIDTable 45. Voltage Regulator VR 12.5 Voltage Identification Electrical Specifications-Processorcontinued continuedProcessor-Electrical Specifications continuedcontinued Electrical Specifications-Processor continuedcontinued Processor-Electrical Specifications continued7.4 Reserved or Unused Signals 7.5 Signal GroupsSignal Groups DDR3 / DDR3L Data Signals DDR3 / DDR3L Reference Voltage SignalsPower / Ground / Other DDR3 / DDR3L Compensation7.6 Test Access Port TAP Connection 7.7 DC SpecificationsPCI Express* Graphics Digital Media Interface DMI7.8 Voltage and Current Specifications Processor-Electrical Specificationscontinued Electrical Specifications-Processor DDR3 / DDR3L Signal Group DC Specifications VCCIOOUT, VCOMPOUT, and VCCIOTERMProcessor-Electrical Specifications continuedDigital Display Interface Group DC Specifications Electrical Specifications-Processorembedded DisplayPort* eDP* Group DC Specifications CMOS Signal Group DC SpecificationsGTL Signal Group and Open Drain Signal Group DC Specifications Processor-Electrical Specifications7.8.1 Platform Environment Control Interface PECI DC Characteristics PCI Express* DC SpecificationsElectrical Specifications-Processor continued7.8.2 Input Device Hysteresis Figure 23. Input Device HysteresisProcessor-Electrical Specifications 8.0 Package Mechanical Specifications 8.2 Package Loading SpecificationsFigure 24. Processor Package Assembly Sketch 8.1 Processor Component Keep-Out Zone8.4 Package Insertion Specifications 8.5 Processor Mass SpecificationProcessor Loading Specifications 8.3 Package Handling Guidelines8.7 Processor Markings 8.8 Processor Land CoordinatesProcessor Materials Figure 25. Processor Top-Side Markings8.9 Processor Storage Specifications Processor Storage SpecificationsFigure 26. Processor Package Land Coordinates Processor-Package Mechanical SpecificationsPackage Mechanical Specifications-Processor RHsustained storageTIMEsustained storage 9.0 Processor Ball and Signal Information Processor Ball List by Signal NameProcessor Ball and Signal Information-Processor continuedcontinued continuedProcessor-Processor Ball and Signal Information continuedcontinued continuedSignal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #continued continuedcontinued AU20Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #