Intel CM8063701159502, CM8064601466200 Coordination of Core Power States at the Package Level

December 2013 Order No.: 328897-004

Processor—Power Management

—For package C-states, the processor is not required to enter C0 state before entering any other C-state.

—Entry into a package C-state may be subject to auto-demotion – that is, the processor may keep the package in a deeper package C-state than requested by the operating system if the processor determines, using heuristics, that the deeper C-state results in better power/performance.

The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following:

•If a core break event is received, the target core is activated and the break event message is forwarded to the target core.

—If the break event is not masked, the target core enters the core C0 state and the processor enters package C0 state.

—If the break event is masked, the processor attempts to re-enter its previous package state.

•If the break event was due to a memory access or snoop request,

—But the platform did not request to keep the processor in a higher package C- state, the package returns to its previous C-state.

—And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C- state.

The following table shows package C-state resolution for a dual-core processor. The following figure summarizes package C-state transitions.

Table 19.	Coordination of Core Power States at the Package Level
	Package C-State				Core 1
			C0	C1	C3	C6	C7
		C0	C0	C0	C0	C0	C0
		C1	C0	C11	C11	C11	C11
	Core 0	C3	C0	C11	C3	C3	C3
		C6	C0	C11	C3	C6	C6
		C7	C0	C11	C3	C6	C7

Note: 1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 56