Intel BX80646I34130 manual Processor Power Signals, Sense Signals, Signal Description-Processor

Signal Description—Processor

6.11Processor Power Signals

Table 41.	Processor Power Signals
	Signal Name	Description	Direction / Buffer
			Type
	VCC	Processor core power rail.	Ref
	VCCIO_OUT	Processor power reference for I/O.	Ref
	VDDQ	Processor I/O supply voltage for DDR3.	Ref
	VCOMP_OUT	Processor power reference for PEG/Display RCOMP.	Ref
	VIDSOUT	VIDALERT#, VIDSCLK, and VIDSCLK comprise a three	Input GTL/ Output Open
		signal serial synchronous interface used to transfer	Drain
	VIDSCLK
		power management information between the	Output Open Drain
	VIDALERT#	processor and the voltage regulator controllers.	Input CMOS

6.12Sense Signals

Table 42.	Sense Signals
	Signal Name	Description	Direction /
			Buffer Type
	VCC_SENSE	VCC_SENSE and VSS_SENSE provide an isolated, low-	O
		impedance connection to the processor input VCC voltage
	VSS_SENSE	and ground. The signals can be used to sense or measure	A
		voltage near the silicon.

6.13Ground and Non-Critical to Function (NCTF) Signals

Table 43.	Ground and Non-Critical to Function (NCTF) Signals
	Signal Name	Description	Direction /
			Buffer Type
	VSS	Processor ground node	GND
	VSS_NCTF	Non-Critical to Function: These pins are for package	—
		mechanical reliability.

6.14Processor Internal Pull-Up / Pull-Down Terminations

Table 44.	Processor Internal Pull-Up / Pull-Down Terminations
	Signal Name	Pull Up / Pull Down	Rail	Value
	BPM[7:0]	Pull Up	VCCIO_TERM	40–60 Ω
	PREQ#	Pull Up	VCCIO_TERM	40–60 Ω
	TDI	Pull Up	VCCIO_TERM	30–70 Ω
	TMS	Pull Up	VCCIO_TERM	30–70 Ω
	CFG[17:0]	Pull Up	VCCIO_OUT	5–8 kΩ
	CATERR#	Pull Up	VCCIO_TERM	30–70 Ω

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	89