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Intel CM8063701212200 manual 2.5.1 3D and Video Engines for Graphics Processing, 3D Pipeline

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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Figure 5. Processor Graphics Controller Unit Block Diagram

Interfaces—Processor

Figure 5. Processor Graphics Controller Unit Block Diagram

2.5.13D and Video Engines for Graphics Processing

The Gen 7.5 3D engine provides the following performance and power-management enhancements.

3D Pipeline

The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine.

3D Engine Execution Units

•Supports up to 20 EUs. The EUs perform 128-bit wide execution per clock.

•Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing.

Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013	Datasheet – Volume 1 of 2
Order No.: 328897-004	29

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Intel CM8063701212200 2.5.1 3D and Video Engines for Graphics Processing, Processor Graphics Controller Unit Block Diagram

Contents

December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 4.0 Power Management ContentsRevision History 1.0 Introduction5.0 Thermal Management 6.0 Signal DescriptionProcessor-Contents 8.0 Package Mechanical Specifications 7.0 Electrical Specifications9.0 Processor Ball and Signal Information 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 Introduction1.1 Supported Technologies Figure 1. Platform Block DiagramProcessor Platform Controller Hub PCH1.2 Interfaces 1.3 Power Management SupportProcessor Core System1.5 Package Support 1.4 Thermal Management Support1.6 Terminology Terminologycontinued with Virtual Machine Monitor software, enables multiple, robust independent softwareProcessor-Introduction Term Introduction-ProcessorDescription continuedRelated Documents 1.7 Related DocumentsProcessor-Introduction DocumentIntroduction-Processor specificationsDocument Document2.1 System Memory Interface 2.0 InterfacesProcessor DIMM Support by Product Supported UDIMM Module Configurations2.1.1 System Memory Technology Supported DDR3 / DDR3L System Memory Timing Support Supported SO-DIMM Module Configurations AIO Only2.1.2 System Memory Timing Support Dual-Channel Mode - Intel Flex Memory Technology Mode Single-Channel ModeDual-Channel Symmetric Mode 2.1.3 System Memory Organization ModesJust-in-Time Command Scheduling 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsCommand Overlap 2.1.3.1 System Memory Frequency2.2 PCI Express* Interface Table 7. PCI Express* Supported Configurations in Desktop Products2.2.1 PCI Express* Support 2.1.3.3 Data Scrambling2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Lanes Connection PCI Express* Related Register Structures in the ProcessorPCI Express* Port Figure 4. PCI Express* Typical Operation 16 Lanes Mapping 2.3 Direct Media Interface DMI1 X 4 Controller 1 X 8 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics2.5.1 3D and Video Engines for Graphics Processing Figure 5. Processor Graphics Controller Unit Block Diagram3D Pipeline 3D Engine Execution UnitsGeometry Shader GS Stage Vertex Shader VS StageClip Stage Strips and Fans SF StageLogical 128-Bit Fixed BLT and 256 Fill Engine 2.6 Digital Display Interface DDI2.5.2 Multi Graphics Controllers Multi-Monitor Support Figure 6. Processor Display Architecture Sink Device Source DeviceDisplayPort Figure 7. DisplayPort* OverviewHDMI Sink HDMI SourceFigure 8. HDMI* Overview HDMI Txembedded DisplayPort Multiple Display ConfigurationsIntegrated Audio Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.8.1 PECI Bus Architecture 2.7 Intel Flexible Display Interface Intel FDI2.8 Platform Environmental Control Interface PECI PECI Figure 9. PECI Host-Clients Connection ExampleHost / Originator PECI Client3.1 Intel Virtualization Technology Intel VT 3.0 TechnologiesIntel VT-x Objectives ing=VTIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology Intel Turbo Boost Technology 2.0 Frequency 3.4 Intel Turbo Boost Technology3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 Intel Secure Key 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIPCLMULQDQ Instruction 3.8 Intel 64 Architecture x2APIC 3.11 Supervisor Mode Execution Protection SMEP 3.9 Power Aware Interrupt Routing PAIR3.10 Execute Disable Bit Figure 11. Processor Power States 4.0 Power ManagementNote Power states availability may vary between the different SKUs S0 - Processor Fully powered on full on mode / connected standby modeSystem States 4.1 Advanced Configuration and Power Interface ACPI States SupportedProcessor Core / Package State Support Integrated Memory Controller States4.2.1 Enhanced Intel SpeedStep Technology Key Features 4.2 Processor Core Power ManagementDirect Media Interface DMI States G, S, and C Interface State CombinationsFigure 12. Idle Power Management Breakdown of the Processor Cores 4.2.2 Low-Power Idle StatesThread ThreadFigure 13. Thread and Core C-State Entry and Exit 4.2.3 Requesting Low-Power Idle StatesCoordination of Thread Power States at the Core Level Core C0 State 4.2.4 Core C-State RulesCore C1/C1E State Core C3 StateCore C6 State 4.2.5 Package C-StatesCore C7 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Package C1/C1E State Figure 14. Package C-State Entry and ExitPackage C0 State Package C3 State Package C2 StatePackage C6 State Package C7 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power-Down4.3.2.1 Initialization Role of CKE 4.5 Direct Media Interface DMI Power Management 4.4 PCI Express* Power Management4.3.3 DRAM Running Average Power Limitation RAPL 4.3.4 DDR Electrical Power Gating EPG4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6 Graphics Power Management4.6.2 Graphics Render C-State 4.6.3 Intel Graphics Dynamic FrequencyThermal Management-Processor 5.0 Thermal Management5.1 Desktop Processor Thermal Profiles Desktop Processor Thermal SpecificationsTemperature on page Processor-Thermal ManagementTCASE = 0.33 * Power + 5.1.1 Processor PCG 2013D Thermal ProfileTTV Power W CaseProcessor-Thermal Management 5.1.2 Processor PCG 2013C Thermal Profilecontinued continuedcontinued 5.1.3 Processor PCG 2013B Thermal ProfileThermal Management-Processor Processor-Thermal Management 5.1.4 Processor PCG 2013A Thermal Profile5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS 5.2 Thermal MetrologyMeasure TCASE at the geometric center of the package 37.5 37.5ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Thermal Margin Slope 5.5 Processor TemperatureFigure 21. Digital Thermal Sensor DTS Thermal Profile Definition Frequency Control 5.6 Adaptive Thermal MonitorImmediate Transition to Combined TM1 and TM2 Critical Temperature FlagClock Modulation PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.9 Intel Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power Control6.1 System Memory Interface Signals 6.0 Signal DescriptionSignal Description Buffer Types Memory Channel A SignalsSignal Description-Processor Memory Channel B SignalsWrite Enable Control Signal This signal is used with continuedMemory Reference and Compensation Signals 6.2 Memory Reference and Compensation SignalsProcessor-Signal Description DDR3/DDR3L Reference Voltage This signal is used asReset and Miscellaneous Signals 6.3 Reset and Miscellaneous SignalsSignal Description-Processor CFG3 MSR Privacy Bit Feature6.5 Display Interface Signals 6.4 PCI Express*-Based Interface SignalsPCI Express* Graphics Interface Signals Display Interface Signals6.8 Testability Signals 6.7 Phase Locked Loop PLL SignalsPhase Locked Loop PLL Signals Testability Signals6.10 Power Sequencing Signals 6.9 Error and Thermal Protection SignalsError and Thermal Protection Signals Power Sequencing Signals6.12 Sense Signals 6.11 Processor Power Signals6.13 Ground and Non-Critical to Function NCTF Signals Processor Power Signals7.2 Power and Ground Lands 7.0 Electrical Specifications7.1 Integrated Voltage Regulator 7.3 VCC Voltage Identification VIDElectrical Specifications-Processor Table 45. Voltage Regulator VR 12.5 Voltage Identificationcontinued continuedcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued continued Processor-Electrical SpecificationsSignal Groups 7.4 Reserved or Unused Signals7.5 Signal Groups DDR3 / DDR3L Reference Voltage Signals DDR3 / DDR3L Data SignalsPower / Ground / Other DDR3 / DDR3L Compensation7.7 DC Specifications 7.6 Test Access Port TAP ConnectionPCI Express* Graphics Digital Media Interface DMIcontinued 7.8 Voltage and Current SpecificationsProcessor-Electrical Specifications Electrical Specifications-Processor VCCIOOUT, VCOMPOUT, and VCCIOTERM DDR3 / DDR3L Signal Group DC SpecificationsProcessor-Electrical Specifications continuedElectrical Specifications-Processor Digital Display Interface Group DC SpecificationsCMOS Signal Group DC Specifications embedded DisplayPort* eDP* Group DC SpecificationsGTL Signal Group and Open Drain Signal Group DC Specifications Processor-Electrical SpecificationsPCI Express* DC Specifications 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsElectrical Specifications-Processor continuedProcessor-Electrical Specifications 7.8.2 Input Device HysteresisFigure 23. Input Device Hysteresis 8.2 Package Loading Specifications 8.0 Package Mechanical SpecificationsFigure 24. Processor Package Assembly Sketch 8.1 Processor Component Keep-Out Zone8.5 Processor Mass Specification 8.4 Package Insertion SpecificationsProcessor Loading Specifications 8.3 Package Handling Guidelines8.8 Processor Land Coordinates 8.7 Processor MarkingsProcessor Materials Figure 25. Processor Top-Side MarkingsProcessor Storage Specifications 8.9 Processor Storage SpecificationsFigure 26. Processor Package Land Coordinates Processor-Package Mechanical SpecificationsTIMEsustained storage Package Mechanical Specifications-ProcessorRHsustained storage Processor Ball List by Signal Name 9.0 Processor Ball and Signal Informationcontinued Processor Ball and Signal Information-Processorcontinued continuedcontinued Processor-Processor Ball and Signal Informationcontinued continuedSignal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #continued continuedcontinued AU20Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #