Intel BX80646I34130, BX80637I73770K embedded DisplayPort* eDP* Group DC Specifications, continued

Models: BX80633I74960X BX80646I34130 BX80646I54430 BX80646I74770K BX80646I74770 BX80646I54570S BX80646I74770S BXF80646I74770K CM8063701159502 CM8063701212200 BX80637I73770K CM8064601466003 CM8064601466200

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embedded DisplayPort* (eDP*) Group DC Specifications
December 2013 Order No.: 328897-004

Processor—Electrical Specifications

Table 52.

embedded DisplayPort* (eDP*) Group DC Specifications

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

VIL

HPD Input Low Voltage

0.02

0.21

V

 

 

 

 

 

 

 

 

VIH

HPD Input High Voltage

0.84

1.05

V

 

 

 

 

 

 

 

 

VOL

eDP_DISP_UTIL Output Low Voltage

0.1*VCC

V

 

VOH

eDP_DISP_UTIL Output High Voltage

0.9*VCC

V

 

RUP

eDP_DISP_UTIL Internal pull-up

100

Ω

 

 

 

 

 

 

 

 

RDOWN

eDP_DISP_UTIL Internal pull-down

100

Ω

 

 

 

 

 

 

 

 

Vaux(Tx)

Aux peak-to-peak voltage at

0.39

1.38

V

 

transmitting device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vaux(Rx)

Aux peak-to-peak voltage at receiving

0.32

1.36

V

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

eDP_RCOMP

COMP Resistance

24.75

25

25.25

Ω

 

DP_RCOMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1. COMP resistance is to VCOMP_OUT.

 

 

 

 

 

 

 

 

 

 

 

Table 53.

CMOS Signal Group DC Specifications

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Max

Units

Notes1

 

VIL

Input Low Voltage

VCCIO_OUT* 0.3

V

2

 

 

 

 

 

 

 

 

VIH

Input High Voltage

VCCIO_OUT* 0.7

V

2, 4

 

 

 

 

 

 

 

 

VOL

Output Low Voltage

VCCIO_OUT * 0.1

V

2

 

 

 

 

 

 

 

 

VOH

Output High Voltage

VCCIO_OUT * 0.9

V

2, 4

 

 

 

 

 

 

 

 

RON

Buffer on Resistance

23

73

Ω

 

 

 

 

 

 

 

 

 

ILI

Input Leakage

±150

μA

3

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

 

 

2. The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.

 

 

3. For VIN between “0” V and VCCIO_OUT. Measured when the driver is tri-stated.

 

 

 

4. VIH and VOH may experience excursions above VCCIO_OUT. However, input signal drivers must

 

comply with the signal quality specifications.

 

 

 

 

 

 

 

 

 

 

Table 54.

GTL Signal Group and Open Drain Signal Group DC Specifications

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Max

 

Units

Notes1

 

VIL

Input Low Voltage (TAP, except

VCCIO_TERM * 0.6

 

V

2

 

TCK)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH

Input High Voltage (TAP, except

VCCIO_TERM * 0.72

 

V

2, 4

 

TCK)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low Voltage (TCK)

VCCIO_TERM * 0.4

 

V

2

 

 

 

 

 

 

 

 

 

VIH

Input High Voltage (TCK)

VCCIO_TERM * 0.8

 

V

2, 4

 

 

 

 

 

 

 

 

 

VHYSTERESIS

Hysteresis Voltage

VCCIO_TERM * 0.2

 

V

 

 

 

 

 

 

 

 

 

RON

Buffer on Resistance (TDO)

12

28

 

Ω

 

 

 

 

 

 

 

 

 

VIL

Input Low Voltage (other GTL)

VCCIO_TERM * 0.6

 

V

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

continued...

Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2 102

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Intel BX80646I34130 embedded DisplayPort* eDP* Group DC Specifications, CMOS Signal Group DC Specifications, continued