PCI-2513 User's Guide Specifications

35

Input sequencer

Analog, digital, and counter inputs can be scanned based on either an internal programmable timer or an

external clock source.

Table 5. Input sequencer specifications
Scan clock sources: two (Note 3) Internal:
Analog channels from 1 µs to 1 sec in 20.83 ns steps.
Digital channels and counters from 83.33 ns to 1 sec in 20.83 ns steps.
External. TTL-level input:
Analog channels down to 1 µs minimum
Digital channels and counters down to 83 ns minimum
Programmable parameters per scan Programmable channels (random order)
Programmable gain
Depth 512 locations
Onboard channel-to-channel scan
rate
Analog: 1 MHz maximum
Digital: 12 MHz
External acquisition scan clock
input maximum rate
1.0 MHz
Clock signal range: Logical zero: 0 V to 0.8 V
Logical one: 2.4 V to 5.0 V
Minimum pulse width 50 ns high, 50 ns low
Note 3: The maximum scan clock rate is the inverse of the minimum scan period. The minimum scan period

is equal to 1 µs times the number of analog channels. If a scan contains only digital channels then

the minimum scan period is 83 ns times the number of digital channels.

Trigger sources and modes
Table 6. Trigger sources and modes
Input scan
trigger
sources
Single channel analog hardware trigger
Single channel analog software trigger
External-single channel digital trigger (TTL TRG input)
Digital pattern trigger
Counter/totalizer trigger
Single channel analog hardware trigger: The first analog input channel in the scan is the analog trigger channel.
Input signal range: -10 V to +10 V maximum
Trigger level: Programmable (12-bit resolution)
Latency: 350 ns typical
Accuracy: ±0.5% of reading, ±2 mV offset maximum
Noise: 2 mV RMS typical
Single channel analog software trigger: The first analog input channel in the scan is the analog trigger channel.
Input signal range: Anywhere within range of the trigger channel
Trigger level: Programmable (16-bit resolution)
Latency: One scan period (maximum)
External-single channel digital trigger (TTL trigger input):
Input signal range: -15 V to +15 V maximum
Trigger level: TTL-level sensitive
Minimum pulse width: 50 ns high, 50 ns low
Latency: One scan period maximum
Digital pattern triggering: 8-bit or 16-bit pattern triggering on any of the digital ports. Programmable for
trigger on equal, not equal, above, or below a value. Individual bits can be masked for "don’t care" condition.
Latency: One scan period, max
Input scan
triggering
modes
Counter/totalizer triggering: Counter/totalizer inputs can trigger an acquisition. User can select to trigger on a
frequency or on total counts that are equal, not equal, above, or below a value, or within/outside of a window
rising/falling edge.
Latency: One scan period, maximum