▍System Assembly
| Memory Population Rules |
1 DIMM | CPU1_DIMM1 (Channel A0) |
2 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) |
3 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) |
4 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) |
5 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) |
6 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) |
7 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) |
8 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) |
9 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) + |
| CPU1_DIMM3 (Channel C0) |
10 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) + |
| CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0) |
11 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) + |
| CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0) + |
| CPU1_DIMM6 (Channel C1) |
12 DIMMs | CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) + |
| CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) + |
| CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) + |
| CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) + |
| CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0) + |
| CPU1_DIMM6 (Channel C1) + CPU2_DIMM6 (Channel C1) |