Advance DRAM Configuration
Press <Enter> to enter the
DRAM Timing Mode
This field has the capacity to automatically detect the DRAM timing. If you set this field to [DCT 0], [DCT 1] or [Both], some fields will appear and selectable. DCT 0 controls channel A and DCT1 controls channel B.
DRAM Drive Strength
This item allows you to control the memory data bus’ signal strength. Increasing the drive strength of the memory bus can increase stability during overclock- ing.
DRAM Advance Control
This field has the capacity to automatically detect the advanced DRAM timing. If you set this field to [DCT 0], [DCT 1] or [Auto], some fields will appear and selectable.
1T/2T Memory Timing
When the DRAM Timing Mode is set to [Manual], the field is adjustable. This field controls the command rate. Selecting [1T] makes DRAM signal controller to run at 1 clock cycle rate. Selecting [2T] makes DRAM signal controller run at 2 clock cycles rate.
DCT Unganged Mode
This feature is used to Integrate two
Bank Interleaving
Bank Interleaving is an important parameter for improving overclocking capabil- ity of memory. It allows system to access multiple banks simultaneously.
Power Down Enable
This is a memory
MemClk Tristate C3/ATLVID
This setting allows you to enable/disable the MemClk Tristating during C3 and
ATLVID.
Adjusted DRAM Frequency (MHz)
It shows the adjusted memory frequency.
HT Link Control
Press <Enter> to enter the
HT Link Speed Auto
Setting to [Enabled], the system will detect the HT link speed automatically.
HT Link Speed
This item allows you to set the
Adjust
This item allows you to adjust the
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