Chapter 3 Hardware Overview
AT-MIO/AI E Series User Manual 3-2
National Instruments Corporation

Figure 3-2 shows the block diagram for the AT-MIO-64E-3.

Figure 3-2. AT-MIO-64E-3 Block Diagram

Timing
PFI / Trigger
I/O Connector
3
RTSI BusAT – I/O Channel
Digital I/O (8)
12-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
NI-PGIA
Gain
Amplifier
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF
Calibration
DACs
Dither
Circuitry
Trigger
Analog
Trigger
Circuitry
2
Trigger Level
DACs
6Calibration
DACs
DAC0
DAC1
3
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(32)
(32)
DAC
FIFO
8
Data (16)
AI Control
Data (16)
Analog
Input
Control
EEPROM
Control DMA
Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control
Bus
Interface
IRQDMA
Data
Transceivers
AO Control
ADC
FIFO