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National Instruments NI 6238, NI 6239 PXI_CLK10, PXI Triggers, PXI_STAR Trigger, PXI_STAR Filters

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Chapter 10 Digital Routing and Clock Generation

NI 6238/6239 User Manual 10-8 ni.com

PXI_CLK10

PXI_CLK10 is a common low-skew 10MHz clock reference clock for

synchronization of multiple modules in a PXI measurement or control

system. The PXI backplane is responsible for generating PXI_CLK10

independently to each peripheral slot in a PXI chassis.

PXI Triggers

A PXI chassis provides eight bused trigger lines to each module in a

system. Triggers may be passed from one module to another, allowing

precisely timed responses to asynchronous external events that are being

monitored or controlled. Triggers can be used to synchronize the operation

of several different PXI peripheral modules.

On M Series devices, the eight PXI trigger signals are synonymous with

RTSI<0..7>.

Note that in a PXI chassis with more than eight slots, the PXI trigger lines

may be divided into multiple independent buses. Refer to the

documentation for your chassis for details.

PXI_STAR Trigger

In a PXI system, the Star Trigger bus implements a dedicated trigger line

between the first peripheral slot (adjacent to the system slot) and the other

peripheral slots. The Star Trigger can be used to synchronize multiple

devices or to share a common trigger signal among devices.

A Star Trigger controller can be installed in this first peripheral slot to

provide trigger signals to other peripheral modules. Systems that do not

require this functionality can install any standard peripheral module in this

first peripheral slot.

An M Series device receives the Star Trigger signal (PXI_STAR) from a

Star Trigger controller. PXI_STAR can be used as an external source for

many AI, AO, and counter signals.

An M Series device is not a Star Trigger controller. An MSeries device

may be used in the first peripheral slot of a PXI system, but the system will

not be able to use the Star Trigger feature.

PXI_STAR Filters

You can enable a programmable debouncing filter on each PFI, RTSI, or

PXI_STAR signal. When the filters are enabled, your device samples the

Contents

Main Page Important Information Warranty Copyright Trademarks Patents Page Contents Chapter 4 Analog Input Chapter 5 Analog Output Chapter 6 Digital Input and Output Chapter 7 Counters Page Chapter 8 PFI Chapter 9 Isolation and Digital Isolators Chapter 10 Digital Routing and Clock Generation Page About This Manual Conventions Related Documentation NI-DAQ NI-DAQmx for Linux NI-DAQmx Base LabVIEW LabWindows/CVI Measurement Studio ANSI C without NI Application Software .NET Languages without NI Application Software Device Documentation and Specifications Training Courses Technical Support on the Web Getting Started Installing NI-DAQmx Installing Other Software Installing the Hardware Device Pinouts Page DAQ System Overview DAQ Hardware DAQ-STC2 Calibration Circuitry Sensors and Transducers Cables and Accessories Custom Cabling Programming Devices in Software Connector Information I/O Connector Signal Descriptions Table 3-1. I/O Connector Signals (Continued) RTSI Connector Pinout Analog Input Analog Input Circuitry Analog Input Range Connecting Analog Current Input Signals Method 1 (20 mA (20 mA)) 216 = 610 nA Figure 4-2. Analog Current Input Connection Method 1 Method 2 Figure 4-3. Analog Current Input Connection Method 2 Analog Input Ground-Reference Settings + Page Configuring AI Ground-Reference Settings in Software Multichannel Scanning Considerations Use Short High-Quality Cabling Minimize Current Step between Adjacent Channels Avoid Scanning Faster Than Necessary Example 1 Example 2 Analog Input Data Acquisition Methods Software-Timed Acquisitions Hardware-Timed Acquisitions Buffered Non-Buffered Analog Input Triggering Field Wiring Considerations Analog Input Timing Signals Page Page AI Sample Clock Signal Using an Internal Source Using an External Source Routing AI Sample Clock Signal to an Output AI Sample Clock Timebase Signal AI Convert Clock Signal Using an Internal Source Page Page AI Convert Clock Timebase Signal AI Hold Complete Event Signal AI Start Trigger Signal Routing AI Start Trigger to an Output Terminal AI Reference Trigger Signal Routing AI Reference Trigger Signal to an Output AI Pause Trigger Signal Routing AI Pause Trigger Signal to an Output Getting Started with AI Applications in Software Analog Output Analog Output Circuitry Analog Output Data Generation Methods Software-Timed Generations Hardware-Timed Generations Non-Buffered Buffered Analog Output Triggering Connecting Analog Current Output Signals Analog Output Timing Signals AO Start Trigger Signal Routing AO Start Trigger Signal to an Output AO Pause Trigger Signal Page Page AO Sample Clock Timebase Signal Getting Started with AO Applications in Software Digital Input and Output I/O Protection Programmable Power-Up States Connecting Digital I/O Signals Logic Conventions Getting Started with DIO Applications in Software Counters Figure 7-1. MSeries Counters Counter Input Applications Counting Edges Single Point (On-Demand) Edge Counting Buffered (Sample Clock) Edge Counting Non-Cumulative Buffered Edge Counting Controlling the Direction of Counting Pulse-Width Measurement Single Pulse-Width Measurement Buffered Pulse-Width Measurement Period Measurement Single Period Measurement Buffered Period Measurement Semi-Period Measurement Single Semi-Period Measurement Buffered Semi-Period Measurement Frequency Measurement Method 1Measure Low Frequency with One Counter Method 1bMeasure Low Frequency with One Counter (Averaged) Figure 7-12. Method 1b Method 2Measure High Frequency with Two Counters Method 3Measure Large Range of Frequencies Using Two Counters Choosing a Method for Measuring Frequency Page Position Measurement Measurements Using Quadrature Encoders X1 Encoding X2 Encoding X4 Encoding Channel Z Behavior Measurements Using Two Pulse Encoders Two-Signal Edge-Separation Measurement Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Counter Output Applications Simple Pulse Generation Single Pulse Generation Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation Pulse Train Generation Continuous Pulse Train Generation Frequency Generation Using the Frequency Generator Frequency Division Pulse Generation for ETS Counter Timing Signals Counter n Source Signal Routing a Signal to Counter n Source Routing Counter n Source to an Output Terminal Counter n Gate Signal Routing a Signal to Counter n Gate Routing Counter n Gate to an Output Terminal Counter n Aux Signal Routing a Signal to Counter n Aux Counter n A, Counter n B, and Counter n Z Signals Routing Signals to A, B, and Z Counter Inputs Routing Counter n Z Signal to an Output Terminal Counter n Up_Down Signal Counter n HW Arm Signal Routing Signals to Counter n HW Arm Input Counter n Internal Output and Counter n TC Signals Routing Counter n Internal Output to an Output Frequency Output Signal Routing Frequency Output to a Terminal Default Counter Terminals Counter Triggering Arm Start Trigger Start Trigger Pause Trigger Other Counter Features Cascading Counters Counter Filters Prescaling Duplicate Count Prevention Example Application That Works Correctly (No Duplicate Counting) Example Application That Works Incorrectly (Duplicate Counting) Example Application That Prevents Duplicate Count When To Use Duplicate Count Prevention Enabling Duplicate Count Prevention in NI-DAQmx Synchronization Modes 80 MHz Source Mode Other Internal Source Mode External Source Mode PFI Using PFI Terminals as Timing Input Signals Exporting Timing Output Signals Using PFI Terminals Using PFI Terminals as Static Digital Inputs and Outputs Connecting PFI Input Signals PFI Filters I/O Protection Programmable Power-Up States Connecting Digital I/O Signals Figure 8-5. NI 6238 Digital I/O Connections (DO Source) Page Isolation and Digital Isolators Digital Isolation Benefits of an Isolated DAQ Device Reducing Common-Mode Noise Digital Routing and Clock Generation Clock Routing 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase External Reference Clock 10 MHz Reference Clock Synchronizing Multiple Devices Real-Time System Integration Bus (RTSI) RTSI Connector Pinout Using RTSI as Outputs Using RTSI Terminals as Timing Input Signals RTSI Filters PXI Clock and Trigger Signals PXI_CLK10 PXI Triggers PXI_STAR Trigger PXI_STAR Filters Page Page Bus Interface DMA Controllers PXI Considerations PXI Clock and Trigger Signals PXI and PXI Express Using PXI with CompactPCI Data Transfer Methods Direct Memory Access (DMA) Interrupt Request (IRQ) Programmed I/O Changing Data Transfer Methods between DMA and IRQ Triggering Triggering with a Digital Source Page A Device-Specific Information NI 6238 NI 6238 Pinout Figure A-1. NI6238 Pinout Table A-1. NI6238 Device Default NI-DAQmx Counter/Timer Pins NI 6238 Specifications NI 6238 Accessory and Cabling Options Screw Terminal RTSI NI 6239 Figure A-2. NI6239 Pinout Table A-2. NI6239 Device Default NI-DAQmx Counter/Timer Pins NI 6239 Specifications NI 6239 Accessory and Cabling Options Screw Terminal RTSI Page B Troubleshooting Analog Input Analog Output Counters C Technical Support and Professional Services Page Glossary Numbers/Symbols A Page B C Page D Page E F G H I Page K L M N O P Q R S Page T U V Page Index Symbols Numerics A B C D E F G H I K L M N O P Q R S T