National Instruments PCI-1200 The GATE and OUT signals in Figure3-16 are referenced to the rising edge of the CLK signal.

Chapter 3 Signal Connections
PCI-1200 User Manual 3-26 © National Instruments Corporation
•82C53 digital output specifications (referenced to DGND):
–Voh output logic high voltage 3.7 V min —
–Vol output logic low voltage —0.45 V max
–Ioh output source current, at Voh —–0.92 mA max
–Iol output sink current, at Vol —2.1 mA max
Figure 3-16 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the 82C53 OUT output signals.
Figure 3-16. General Purpose Timing Signals
The GATE and OUT signals in Figure3-16 are referenced to the rising edge
of the CLK signal.
tsc tpwh tpwl
tgsu tgh
tgwh tgwl
toutc
toutg
CLK
GATE
OUT
VOH
VIH
VIL
VIH
VOL
VIL
tsc
tpwh
tpwl
tgsu
tgh
tgwh
tgwl
toutc
toutg
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
380 ns minimum
230 ns minimum
150 ns minimum
100 ns minimum
50 ns minimum
150 ns minimum
100 ns minimum
300 ns maximum
400 ns maximum