Chapter 3 Hardware Overview
IMAQ PCI-1428 User Manual 3-2 ni.com

Figure 3-1. PCI-1428 Block Diagram

Camera Link and PCI-1428

The PCI-1428 supports the Camera Link Base configuration, as well as the

8-bit × 4 mode of the Camera Link Medium configur ation.

Base Configuration

The Camera Link Base configuration places 24 data bits and four enable

signals (Frame Valid, Line Valid, Data Valid, and a spare) on a single

Channel Link part and cable.

The Base configuration includes asynchronous serial transmission as well

as four digital camera control lines for controlling exposure time, frame

rates, and other camera control signals. These four control lines are

Data
26-Pin MDR Connector
Channel
Link
Receiver
Enables
Pixel
Clock
Camera
Control
UART
PCI Bus
PCI Interface
and
Scatter-Gather
DMA Controllers
Data IMAQ SDRAM
Interface
Synchronous Dynamic RAM
Advanced
Triggering
and Timing
Acquisition, Scaling,
ROI, and Control
External Triggers
Pixel Clock and Camera Enables
RTSI Bus
LUT LUT Data
Data
Differential
Converter
68-Pin VHDCI
Serial
Control
Enables
Pixel
Clock
Channel
Link
Receiver
Data