© National Instruments Corporation I-1 IMAQ PCI-1428 User Manual
Index

Numbers

68-pin VHDCI connector, 4-2 to 4-3
cable specifications, B-1
overview, 4-2
pin assignments (figure), 4-3

A

acquisition, scaling, and region-of-interest (ROI)
circuitry, 3-5
acquisition start conditions, 3-6
acquisition window control, 3-6
active pixel region (acquisition
window),3-6
region of interest, 3-6
scaling down circuitry, 3-6

B

Base configuration, Camera Link, 3-2 to 3-3
block diagram of IMAQ PCI-1428 (figure) , 3-2
bus master PCI interface, 3-5

C

cabling, B-1 to B-2
68-pin VHDCI cable specifications, B-1
Camera Link cables, B-1 to B-2
Camera Link
Base configuration, 3-2 to 3-3
cabling
description, B-1 to B-2
ordering information, B-2
interfacing with image acquisition
devices, 1-2 to 1-3
Medium configuration, 3-3
overview, 1-2
CC<4..1>± signal (table), 4-4
CHASSIS-GND signal (table), 4-3
clock signals
XCLK±<1..0>± signal (table), 4-4
YCLK±<1..0>± signal (table), 4-4
clock specifications, A-1
configuration
Camera Link
Base configuration, 3-2 to 3-3
Medium configuration, 3-3
flowchart (figure), 2-3
general information, 2-7
setting up IMAQ PCI-1428, 2-2 to 2-3
connectors
68-pin VHDCI connector, 4-2 to 4-3
MDR 26-pin connector, 4-2
PCI-1428 connectors (figure), 4-1
signal description (table), 4-3 to 4-4
conventions used in manual, vi
customer education, C-1

D

data formatter, multiple-tap, 3-4
data transmission, 3-3
delayed acquisition start conditions, 3-6
DGND signal (table), 4-3
digital I/O lines, using trigger lines for
(note),1-1
DMA controllers, 3-5

E

environment specifications, A-2
equipment, optional, 2-2
external connection specifications, A-1