Glossary
© National Instruments Corporation G-3 VXI-1394 User Manual for Windows
block-mode transfer An uninterrupted transfer of data elements in which the master sources only
the first address at the beginning of the cycle. The slave is then responsible
for incrementing the address on subsequent transfers so that the next
element is transferred to or from the proper storage location. A VME data
transfer may have no more than 256 elements.
bus The group of conductors that interconnect individual circuitry in a
computer. Typically, a bus is the expansion vehicle to which I/O or other
devices are connected. Examples of buses include the ISAbus, PCI bus,
VXIbus, and VME bus.
bus error An error that signals failed access to an address. Bus errors occur with
low-level accesses to memory and usually involve hardware with bus
mapping capabilities. For example, nonexistent memory, a nonexistent
register, or an incorrect device access can cause a bus error.
bus master A device that is capable of requesting the Data Transfer Bus (DTB) for the
purpose of accessing a slave device.
byte order How bytes are arranged within a word or how words are arranged within
alongword. Motorola ordering stores the most significant byte (MSB) or
word first, followed by the least significant byte (LSB) or word. Intel
ordering stores the LSB or word first, followed by the MSB or word.
CCCelsius.
CLK10 A 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
CMOS Complementary Metal Oxide Semiconductor—a process used in making
chips.